google / open-chipletLinks
☆26Updated 4 years ago
Alternatives and similar repositories for open-chiplet
Users that are interested in open-chiplet are comparing it to the libraries listed below
Sorting:
- ☆30Updated 6 years ago
- CNN accelerator☆27Updated 8 years ago
- ☆78Updated this week
- ☆36Updated 4 years ago
- [DAC 2020] Analysis and Optimization of the Implicit Broadcasts in FPGA HLS to Improve Maximum Frequency☆32Updated 4 years ago
- SAURIA (Systolic-Array tensor Unit for aRtificial Intelligence Acceleration) is an open-source Convolutional Neural Network accelerator b…☆59Updated last year
- NOCulator is a network-on-chip simulator providing cycle-accurate performance models for a wide variety of networks (mesh, torus, ring, h…☆27Updated 2 years ago
- DASS HLS Compiler☆29Updated 2 years ago
- PAAS: A System Level Simulator for Heterogeneous (CPU-FPGA) Computing Systems☆43Updated 4 years ago
- Repo for all activity related to the ODSA Bunch of Wires Specification☆26Updated last year
- A unified simulation platform that combines hardware and software, enabling pre-silicon, full-stack, closed-loop evaluation of your robot…☆44Updated 6 months ago
- Dynamically Reconfigurable Architecture Template and Cycle-level Microarchitecture Simulator for Dataflow AcCelerators☆29Updated 2 years ago
- FleetRec: Large-Scale Recommendation Inference on Hybrid GPU-FPGA Clusters☆17Updated 4 years ago
- Heterogeneous Accelerated Computed Cluster (HACC) Resources Page☆22Updated 2 weeks ago
- Contains FPGA benchmarks for Vivado HLS and Catapult HLS☆26Updated 5 years ago
- CHIPKIT: An agile, reusable open-source framework for rapid test chip development☆42Updated 5 years ago
- Runtime-First FPGA Interchange Routing Contest @ FPGA’24☆33Updated 4 months ago
- HLS project modeling various sparse accelerators.☆12Updated 3 years ago
- Provides the hardware code for the paper "EBPC: Extended Bit-Plane Compression for Deep Neural Network Inference and Training Accelerator…☆24Updated 5 years ago
- ☆29Updated 8 years ago
- Next generation CGRA generator☆114Updated last week
- sram/rram/mram.. compiler☆42Updated 2 years ago
- TensorCore Vector Processor for Deep Learning - Google Summer of Code Project☆22Updated 4 years ago
- dMazeRunner: Dataflow acceleration optimization infrastructure for coarse-grained programmable accelerators☆47Updated 3 years ago
- Virtualized Accelerator Orchestration for Multi-Tenant Workloads☆19Updated 10 months ago
- ☆27Updated 5 years ago
- Circuit-level model for the Capacity-Latency Reconfigurable DRAM (CLR-DRAM) architecture. This repository contains the SPICE models of th…☆14Updated 5 years ago
- RISCV-VP++ is a extended and improved successor of the RISC-V based Virtual Prototype (VP) RISC-V VP. It is maintained at the Institute f…☆40Updated last week
- ☆37Updated 6 months ago
- Introductory examples for using PYNQ with Alveo☆52Updated 2 years ago