Alternatives and similar repositories for eqy

Users that are interested in eqy are comparing it to the libraries listed below

• pulp-platform / morty
  A SystemVerilog source file pickler.
  ☆57Updated 7 months ago
• AUCOHL / Lighter
  An automatic clock gating utility
  ☆48Updated last month
• bespoke-silicon-group / bsg_sv2v
  A tool that converts SystemVerilog to Verilog. Uses Design Compiler, so it is 100% compatible.
  ☆41Updated 2 years ago
• pulp-platform / cheshire-ihp130-o
  ☆44Updated 2 months ago
• Kuree / hgdb
  Hardware generator debugger
  ☆74Updated last year
• tdb-alcorn / chisel-formal
  ☆23Updated 4 years ago
• YosysHQ-GmbH / SVA-AXI4-FVIP
  YosysHQ SVA AXI Properties
  ☆39Updated 2 years ago
• amamory-verification / hw-formal-verif
  Hardware Formal Verification
  ☆15Updated 4 years ago
• ucb-substrate / substrate2
  21st century electronic design automation tools, written in Rust.
  ☆30Updated last week
• povik / yosys-slang
  SystemVerilog frontend for Yosys
  ☆117Updated last week
• ovh / sv2chisel
  (System)Verilog to Chisel translator
  ☆114Updated 3 years ago
• rahulk29 / sram22
  A configurable SRAM generator
  ☆50Updated last week
• Intuity / nexus
  Open source RTL simulation acceleration on commodity hardware
  ☆27Updated 2 years ago
• freechipsproject / ip-contributions
  For contributions of Chisel IP to the chisel community.
  ☆61Updated 6 months ago
• PrincetonUniversity / AutoSVA
  AutoSVA is a tool to automatically generate formal testbenches for unit-level RTL verification. The goal is to, based on annotations made…
  ☆83Updated last year
• openformal / sva_basics
  This repository is compilation of basics of System Verilog Assertions in context of formal verification
  ☆21Updated 6 years ago
• pulp-platform / svase
  ☆32Updated 4 months ago
• MikePopoloski / pyslang
  Python bindings for slang, a library for compiling SystemVerilog
  ☆58Updated 4 months ago
• chipsalliance / espresso
  ☆39Updated last year
• csail-csg / pyverilator
  Python wrapper for verilator model
  ☆84Updated last year
• IntelLabs / pycaliper
  PyCaliper is Python-based tooling infrastructure that allows the verification and synthesis of specifications (properties) for RTL (e.g.,…
  ☆22Updated 4 months ago
• chipsalliance / firrtl-spec
  The specification for the FIRRTL language
  ☆56Updated this week
• ekiwi / rtl-repair
  Fast Symbolic Repair of Hardware Design Code
  ☆23Updated 4 months ago
• dian-lun-lin / RTLflow
  A GPU acceleration flow for RTL simulation with batch stimulus
  ☆110Updated last year
• sgherbst / svinst
  Determines the modules declared and instantiated in a SystemVerilog file
  ☆44Updated 8 months ago
• StanfordAHA / lake
  Lake is a framework for generating synthesizable memory modules from a high-level behavioral specification and widely-available memory ma…
  ☆22Updated last week
• ymherklotz / verismith
  Verilog Fuzzer to test the major simulators and sythesisers by generating random, valid Verilog.
  ☆104Updated 3 weeks ago
• hplp / aes_chisel
  Implementation of the Advanced Encryption Standard in Chisel
  ☆20Updated 3 years ago
• ekiwi / open-source-formal-verification-for-chisel
  ☆11Updated 3 years ago
• grayresearch / CX
  Proposed RISC-V Composable Custom Extensions Specification
  ☆70Updated last year