Equivalence checking with Yosys
☆60Aug 5, 2026Updated last week
Alternatives and similar repositories for eqy
Users that are interested in eqy are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- Random Generator of Btor2 Files☆10Sep 2, 2023Updated 2 years ago
- Collection for submission (Hardware Model Checking Benchmark)☆13Nov 9, 2025Updated 9 months ago
- rIC3 model checker for Hardware Model Checking Competition 2024(HWMCC'24) submission☆12Jul 4, 2025Updated last year
- Yosys RTLIL dialect for MLIR☆24Jun 12, 2025Updated last year
- ☆13Jan 20, 2023Updated 3 years ago
- Wordpress hosting with auto-scaling - Free Trial Offer • AdFully Managed hosting for WordPress and WooCommerce businesses that need reliable, auto-scalable performance. Cloudways SafeUpdates now available.
- ☆18Jul 12, 2024Updated 2 years ago
- Mutation Cover with Yosys (MCY)☆97Aug 5, 2026Updated last week
- The HW-CBMC and EBMC Model Checkers for Verilog☆114Updated this week
- A tutorial for setting up Symbolic Quick Error Detection (SQED) using the model checker, CoSA, on the Ride Core☆11May 24, 2019Updated 7 years ago
- A Coq framework to support structural design and proof of hardware cache-coherence protocols☆15May 7, 2022Updated 4 years ago
- SymbiYosys (sby) -- Front-end for Yosys-based formal verification flows☆537Aug 5, 2026Updated last week
- ☆18Nov 19, 2023Updated 2 years ago
- Code for the paper "LLM Meets Bounded Model Checking: Neuro-symbolic Loop Invariant Inference" at ASE 2024☆30Sep 3, 2024Updated last year
- E-Syn: E-Graph Rewriting with Technology-Aware Cost Functions for Logic Synthesis (DAC 2024)☆45Jul 17, 2024Updated 2 years ago
- Simple, predictable pricing with DigitalOcean hosting • AdAlways know what you'll pay with monthly caps and flat pricing. Enterprise-grade infrastructure trusted by 600k+ customers.
- ☆15Jun 18, 2023Updated 3 years ago
- LLM Evaluation Benchmark on Hardware Formal Verification☆44Apr 3, 2025Updated last year
- ☆15Sep 14, 2020Updated 5 years ago
- Collection of test cases for Yosys☆17Jan 4, 2022Updated 4 years ago
- A collection of tests and benchmarks for the Arc simulation backend of CIRCT☆39Jan 26, 2026Updated 6 months ago
- AMulet 2. - A better AIG Multiplier Examination Tool☆32Dec 23, 2025Updated 7 months ago
- LLM-Assisted Hardware Formal Verification Tool☆113Jul 13, 2026Updated last month
- ABC: System for Sequential Logic Synthesis and Formal Verification☆35Updated this week
- ☆15Feb 6, 2021Updated 5 years ago
- Open source password manager - Proton Pass • AdSecurely store, share, and autofill your credentials with Proton Pass, the end-to-end encrypted password manager trusted by millions.
- CIRCT and Yosys interoperability, demonstrated with CHISEL☆17Feb 3, 2026Updated 6 months ago
- Minimal RISC-V Chisel design strictly reflecting the ISA document for verification.☆21Apr 14, 2026Updated 4 months ago
- A fork of Yosys that integrates the CellIFT pass☆14Apr 21, 2026Updated 3 months ago
- SystemVerilog synthesis tool☆235Mar 10, 2025Updated last year
- Arithmetic multiplier benchmarks☆12Nov 13, 2017Updated 8 years ago
- Contract-Aware RTL Code Generation Agents with Temporal Tracing, Slicing and Formal Verification☆23Jan 28, 2026Updated 6 months ago
- A Lean-embedded framework to verify Verilog modules☆15Updated this week
- This is a python repo for flattening Verilog☆20Dec 19, 2025Updated 7 months ago
- Logic optimization and technology mapping tool.☆20Oct 12, 2023Updated 2 years ago
- Deploy to Railway using AI coding agents - Free Credits Offer • AdUse Claude Code, Codex, OpenCode, and more. Autonomous software development now has the infrastructure to match with Railway.
- RISC-V Formal in Chisel☆13Apr 9, 2024Updated 2 years ago
- Research project from UCI's AICPS lab: using GNNs to enable hardware security and prevent hardware trojans☆10Mar 31, 2021Updated 5 years ago
- ☆19Dec 21, 2020Updated 5 years ago
- CoreIR Symbolic Analyzer☆75Oct 27, 2020Updated 5 years ago
- ☆21Jun 12, 2024Updated 2 years ago
- A generic parser and tool package for the BTOR2 format.☆49Sep 18, 2025Updated 10 months ago
- SystemVerilog design elaborator into word-level netlist form☆247Updated this week