YosysHQ / eqyLinks
Equivalence checking with Yosys
☆45Updated 2 weeks ago
Alternatives and similar repositories for eqy
Users that are interested in eqy are comparing it to the libraries listed below
Sorting:
- ☆23Updated 4 years ago
- Fast Symbolic Repair of Hardware Design Code☆25Updated 7 months ago
- 21st century electronic design automation tools, written in Rust.☆31Updated last week
- Verilog Fuzzer to test the major simulators and sythesisers by generating random, valid Verilog.☆110Updated 3 months ago
- (System)Verilog to Chisel translator☆116Updated 3 years ago
- PyCaliper is Python-based tooling infrastructure that allows the verification and synthesis of specifications (properties) for RTL (e.g.,…☆22Updated 2 months ago
- Hardware generator debugger☆75Updated last year
- A configurable SRAM generator☆53Updated this week
- high-performance RTL simulator☆173Updated last year
- AutoSVA is a tool to automatically generate formal testbenches for unit-level RTL verification. The goal is to, based on annotations made…☆88Updated last year
- This is a python repo for flattening Verilog☆19Updated 3 months ago
- fakeram generator for use by researchers who do not have access to commercial ram generators☆37Updated 2 years ago
- A Hardware Pipeline Description Language☆45Updated last month
- ☆40Updated 2 months ago
- A SystemVerilog source file pickler.☆59Updated 10 months ago
- ☆49Updated 4 months ago
- ☆12Updated 4 years ago
- design and verification of asynchronous circuits☆40Updated last month
- CoreIR Symbolic Analyzer☆73Updated 4 years ago
- Open source RTL simulation acceleration on commodity hardware☆29Updated 2 years ago
- Runtime-First FPGA Interchange Routing Contest @ FPGA’24☆33Updated 2 months ago
- ☆18Updated last year
- YosysHQ SVA AXI Properties☆42Updated 2 years ago
- Verification environment for the OpenHW Group's CORE-V High Performance Data Cache controller.☆16Updated 6 months ago
- ILA Model Database☆23Updated 4 years ago
- ☆19Updated last year
- CIRCT-based HLS compilation flows, debugging, and cosimulation tools.☆50Updated 2 years ago
- An automatic clock gating utility☆50Updated 4 months ago
- ☆28Updated 2 weeks ago
- A repository that implements Tywaves: enabling a type-based waveform debugging for Chisel and Tydi-Chisel. Mapping from Chisel level code…☆48Updated 9 months ago