YosysHQ / eqyLinks
Equivalence checking with Yosys
☆43Updated 3 weeks ago
Alternatives and similar repositories for eqy
Users that are interested in eqy are comparing it to the libraries listed below
Sorting:
- A SystemVerilog source file pickler.☆57Updated 7 months ago
- An automatic clock gating utility☆48Updated last month
- A tool that converts SystemVerilog to Verilog. Uses Design Compiler, so it is 100% compatible.☆41Updated 2 years ago
- ☆44Updated 2 months ago
- Hardware generator debugger☆74Updated last year
- ☆23Updated 4 years ago
- YosysHQ SVA AXI Properties☆39Updated 2 years ago
- Hardware Formal Verification☆15Updated 4 years ago
- 21st century electronic design automation tools, written in Rust.☆30Updated last week
- SystemVerilog frontend for Yosys☆117Updated last week
- (System)Verilog to Chisel translator☆114Updated 3 years ago
- A configurable SRAM generator☆50Updated last week
- Open source RTL simulation acceleration on commodity hardware☆27Updated 2 years ago
- For contributions of Chisel IP to the chisel community.☆61Updated 6 months ago
- AutoSVA is a tool to automatically generate formal testbenches for unit-level RTL verification. The goal is to, based on annotations made…☆83Updated last year
- This repository is compilation of basics of System Verilog Assertions in context of formal verification☆21Updated 6 years ago
- ☆32Updated 4 months ago
- Python bindings for slang, a library for compiling SystemVerilog☆58Updated 4 months ago
- ☆39Updated last year
- Python wrapper for verilator model☆84Updated last year
- PyCaliper is Python-based tooling infrastructure that allows the verification and synthesis of specifications (properties) for RTL (e.g.,…☆22Updated 4 months ago
- The specification for the FIRRTL language☆56Updated this week
- Fast Symbolic Repair of Hardware Design Code☆23Updated 4 months ago
- A GPU acceleration flow for RTL simulation with batch stimulus☆110Updated last year
- Determines the modules declared and instantiated in a SystemVerilog file☆44Updated 8 months ago
- Lake is a framework for generating synthesizable memory modules from a high-level behavioral specification and widely-available memory ma…☆22Updated last week
- Verilog Fuzzer to test the major simulators and sythesisers by generating random, valid Verilog.☆104Updated 3 weeks ago
- Implementation of the Advanced Encryption Standard in Chisel☆20Updated 3 years ago
- ☆11Updated 3 years ago
- Proposed RISC-V Composable Custom Extensions Specification☆70Updated last year