Alternatives and similar repositories for eqy:

Users that are interested in eqy are comparing it to the libraries listed below

• pulp-platform / morty
  A SystemVerilog source file pickler.
  ☆56Updated 5 months ago
• AUCOHL / Lighter
  An automatic clock gating utility
  ☆45Updated 8 months ago
• ekiwi / rtl-repair
  Fast Symbolic Repair of Hardware Design Code
  ☆22Updated 2 months ago
• pulp-platform / cheshire-ihp130-o
  ☆34Updated this week
• bespoke-silicon-group / bsg_sv2v
  A tool that converts SystemVerilog to Verilog. Uses Design Compiler, so it is 100% compatible.
  ☆40Updated last year
• rahulk29 / sram22
  A configurable SRAM generator
  ☆47Updated 2 months ago
• povik / yosys-slang
  SystemVerilog frontend for Yosys
  ☆81Updated 2 weeks ago
• ucb-substrate / substrate2
  21st century electronic design automation tools, written in Rust.
  ☆29Updated this week
• ekiwi / open-source-formal-verification-for-chisel
  ☆11Updated 3 years ago
• tdb-alcorn / chisel-formal
  ☆23Updated 4 years ago
• chipsalliance / systemc-compiler
  Intel Compiler for SystemC
  ☆23Updated last year
• Kuree / hgdb
  Hardware generator debugger
  ☆73Updated last year
• grayresearch / CX
  Proposed RISC-V Composable Custom Extensions Specification
  ☆70Updated 10 months ago
• chipsalliance / fpga-interchange-schema
  ☆55Updated 2 years ago
• Nic30 / pyDigitalWaveTools
  Python library for operations with VCD and other digital wave files
  ☆48Updated 9 months ago
• freechipsproject / chisel-cheatsheet
  Chisel Cheatsheet
  ☆33Updated last year
• dian-lun-lin / RTLflow
  A GPU acceleration flow for RTL simulation with batch stimulus
  ☆106Updated last year
• PrincetonUniversity / AutoSVA
  AutoSVA is a tool to automatically generate formal testbenches for unit-level RTL verification. The goal is to, based on annotations made…
  ☆80Updated last year
• csail-csg / pyverilator
  Python wrapper for verilator model
  ☆81Updated last year
• efabless / sky130_sram_macros_old
  ☆36Updated 2 years ago
• pulp-platform / svase
  ☆31Updated 2 months ago
• Intuity / nexus
  Open source RTL simulation acceleration on commodity hardware
  ☆25Updated last year
• chipsalliance / espresso
  ☆38Updated last year
• openformal / sva_basics
  This repository is compilation of basics of System Verilog Assertions in context of formal verification
  ☆20Updated 6 years ago
• sgherbst / svinst
  Determines the modules declared and instantiated in a SystemVerilog file
  ☆43Updated 6 months ago
• YosysHQ / yosys-tests
  Collection of test cases for Yosys
  ☆18Updated 3 years ago
• chipsalliance / f4pga-sdf-timing
  Python library for working Standard Delay Format (SDF) Timing Annotation files.
  ☆28Updated 8 months ago
• IntelLabs / pycaliper
  PyCaliper is Python-based tooling infrastructure that allows the verification and synthesis of specifications (properties) for RTL (e.g.,…
  ☆20Updated 2 months ago
• dh73 / A_Formal_Tale_Chapter_I_AMBA
  AXI Formal Verification IP
  ☆20Updated 3 years ago
• sequencer / arithmetic
  ☆32Updated last week