OpenXiangShan / HuanCun
Open-source high-performance non-blocking cache
☆78Updated this week
Alternatives and similar repositories for HuanCun:
Users that are interested in HuanCun are comparing it to the libraries listed below
- Open source high performance IEEE-754 floating unit☆67Updated last year
- XiangShan Frontend Develop Environment☆55Updated this week
- Modern co-simulation framework for RISC-V CPUs☆139Updated this week
- Open-source non-blocking L2 cache☆37Updated this week
- chipyard in mill :P☆77Updated last year
- A RISC-V Core (RV32I) written in Chisel HDL☆102Updated 9 months ago
- Software tools that support rocket-chip (GNU toolchain, ISA simulator, tests)☆54Updated last year
- A modular, parametrizable, and highly flexible Data Movement Accelerator (DMA)☆139Updated 2 weeks ago
- A Chisel RTL generator for network-on-chip interconnects☆189Updated 2 weeks ago
- IOMMU IP compliant with the RISC-V IOMMU Specification v1.0☆88Updated this week
- This repo includes XiangShan's function units☆18Updated this week
- Open Source Chip Project by University (OSCPU) - Zhoushan Core☆49Updated 2 years ago
- pulp_soc is the core building component of PULP based SoCs☆79Updated 2 weeks ago
- Vector Acceleration IP core for RISC-V*☆172Updated this week
- Unit tests generator for RVV 1.0☆79Updated this week
- ☆82Updated this week
- Microarchitecture implementation of the decoupled vector-fetch accelerator☆150Updated last year
- Provides various testers for chisel users☆100Updated 2 years ago
- ☆32Updated this week
- (System)Verilog to Chisel translator☆112Updated 2 years ago
- Setup scripts and files needed to compile CoreMark on RISC-V☆65Updated 8 months ago
- Vector processor for RISC-V vector ISA☆116Updated 4 years ago
- Spatz is a compact RISC-V-based vector processor meant for high-performance, small computing clusters.☆99Updated this week
- ☆34Updated last month
- ☆63Updated last month
- The batteries-included testing and formal verification library for Chisel-based RTL designs.☆231Updated 7 months ago
- Wrapper for Rocket-Chip on FPGAs☆129Updated 2 years ago
- A dynamic verification library for Chisel.☆147Updated 4 months ago
- The multi-core cluster of a PULP system.☆85Updated last week
- ☆33Updated 8 months ago