Alternatives and similar repositories for HuanCun

Users that are interested in HuanCun are comparing it to the libraries listed below

• OpenXiangShan / fudian
  Open source high performance IEEE-754 floating unit
  ☆72Updated last year
• OpenXiangShan / xs-env
  XiangShan Frontend Develop Environment
  ☆57Updated last week
• OpenXiangShan / CoupledL2
  Open-source non-blocking L2 cache
  ☆43Updated this week
• zero-day-labs / riscv-iommu
  IOMMU IP compliant with the RISC-V IOMMU Specification v1.0
  ☆94Updated 2 months ago
• OpenXiangShan / difftest
  Modern co-simulation framework for RISC-V CPUs
  ☆145Updated last week
• OpenXiangShan / YunSuan
  This repo includes XiangShan's function units
  ☆26Updated this week
• pulp-platform / iDMA
  A modular, parametrizable, and highly flexible Data Movement Accelerator (DMA)
  ☆159Updated last week
• chipsalliance / rocket-tools
  Software tools that support rocket-chip (GNU toolchain, ISA simulator, tests)
  ☆55Updated last year
• ucb-bar / hwacha
  Microarchitecture implementation of the decoupled vector-fetch accelerator
  ☆154Updated last year
• ucb-bar / testchipip
  ☆84Updated 3 weeks ago
• ucb-bar / chiseltest
  The batteries-included testing and formal verification library for Chisel-based RTL designs.
  ☆232Updated 9 months ago
• chipsalliance / playground
  chipyard in mill :P
  ☆78Updated last year
• hushenwei2000 / rvv-atg
  RISC-V Vector (RVV) Automatic Tests Generator with full instructions coverage, including self-checking test and signature test (RISC-V Co…
  ☆15Updated last year
• ucb-bar / constellation
  A Chisel RTL generator for network-on-chip interconnects
  ☆198Updated 3 weeks ago
• carlosedp / chiselv
  A RISC-V Core (RV32I) written in Chisel HDL
  ☆103Updated last month
• IntelLabs / riscv-vector
  Vector Acceleration IP core for RISC-V*
  ☆178Updated 3 weeks ago
• OpenXiangShan / nexus-am
  ☆35Updated this week
• Tang-Haojin / YuQuan
  A RISC-V core running Debian (and a LoongArch core running Linux).
  ☆22Updated last year
• ic-lab-duth / RISC-V-Vector
  Vector processor for RISC-V vector ISA
  ☆119Updated 4 years ago
• pulp-platform / pulp_soc
  pulp_soc is the core building component of PULP based SoCs
  ☆79Updated 2 months ago
• OSCPU / chisel-playground
  ☆67Updated 3 months ago
• ccelio / chisel-style-guide
  A Style Guide for the Chisel Hardware Construction Language
  ☆107Updated 3 years ago
• riscv-boom / riscv-coremark
  Setup scripts and files needed to compile CoreMark on RISC-V
  ☆68Updated 10 months ago
• ucb-bar / saturn-vectors
  Chisel RISC-V Vector 1.0 Implementation
  ☆98Updated 3 weeks ago
• openhwgroup / cv-hpdcache
  RTL sources of the High-Performance L1 Dcache (HPDcache) for OpenHW CV cores
  ☆77Updated this week
• chipsalliance / riscv-vector-tests
  Unit tests generator for RVV 1.0
  ☆85Updated 2 weeks ago
• whutddk / RiftCore
  RiftCore is a 9-stage, single-issue, out-of-order 64-bits RISC-V Core, which supports RV64IMC and 3-level Cache System
  ☆42Updated 2 years ago
• freechipsproject / chisel-testers
  Provides various testers for chisel users
  ☆100Updated 2 years ago
• ovh / sv2chisel
  (System)Verilog to Chisel translator
  ☆114Updated 3 years ago
• chiselverify / chiselverify
  A dynamic verification library for Chisel.
  ☆151Updated 6 months ago