Alternatives and similar repositories for HuanCun

Users that are interested in HuanCun are comparing it to the libraries listed below

• OpenXiangShan / fudian
  Open source high performance IEEE-754 floating unit
  ☆83Updated last year
• pulp-platform / iDMA
  A modular, parametrizable, and highly flexible Data Movement Accelerator (DMA)
  ☆174Updated last month
• OpenXiangShan / CoupledL2
  Open-source non-blocking L2 cache
  ☆47Updated this week
• chipsalliance / playground
  chipyard in mill :P
  ☆78Updated last year
• IntelLabs / riscv-vector
  Vector Acceleration IP core for RISC-V*
  ☆183Updated 3 months ago
• chipsalliance / rocket-tools
  Software tools that support rocket-chip (GNU toolchain, ISA simulator, tests)
  ☆57Updated last year
• OpenXiangShan / xs-env
  XiangShan Frontend Develop Environment
  ☆64Updated last week
• zero-day-labs / riscv-iommu
  IOMMU IP compliant with the RISC-V IOMMU Specification v1.0
  ☆101Updated 3 weeks ago
• OpenXiangShan / difftest
  Modern co-simulation framework for RISC-V CPUs
  ☆148Updated this week
• ucb-bar / hwacha
  Microarchitecture implementation of the decoupled vector-fetch accelerator
  ☆154Updated last year
• ucb-bar / saturn-vectors
  Chisel RISC-V Vector 1.0 Implementation
  ☆108Updated 3 months ago
• pulp-platform / hero
  Heterogeneous Research Platform (HERO) for exploration of heterogeneous computers consisting of programmable many-core accelerators and a…
  ☆111Updated last year
• ovh / sv2chisel
  (System)Verilog to Chisel translator
  ☆116Updated 3 years ago
• pulp-platform / pulp_cluster
  The multi-core cluster of a PULP system.
  ☆106Updated last week
• sequencer / arithmetic
  ☆33Updated 5 months ago
• carlosedp / chiselv
  A RISC-V Core (RV32I) written in Chisel HDL
  ☆103Updated 2 weeks ago
• pulp-platform / tech_cells_generic
  Technology dependent cells instantiated in the design for generic process (simulation, FPGA)
  ☆65Updated 7 months ago
• litmus-tests / litmus-tests-riscv
  RISC-V architecture concurrency model litmus tests
  ☆87Updated 3 months ago
• ucb-bar / riscv-torture
  RISC-V Torture Test
  ☆197Updated last year
• ic-lab-duth / RISC-V-Vector
  Vector processor for RISC-V vector ISA
  ☆126Updated 4 years ago
• pulp-platform / axi_riscv_atomics
  AXI Adapter(s) for RISC-V Atomic Operations
  ☆66Updated 2 weeks ago
• ucb-bar / testchipip
  ☆85Updated 2 months ago
• bluespec / Toooba
  RISC-V Core; superscalar, out-of-order, multi-core capable; based on RISCY-OOO from MIT
  ☆179Updated 3 months ago
• stillwater-sc / RISC-V-TensorCore
  Transactional Verilog design and Verilator Testbench for a RISC-V TensorCore Vector co-processor for reproducible linear algebra
  ☆57Updated 3 years ago
• riscv-boom / riscv-coremark
  Setup scripts and files needed to compile CoreMark on RISC-V
  ☆70Updated last year
• chiselverify / chiselverify
  A dynamic verification library for Chisel.
  ☆154Updated 9 months ago
• ucb-bar / sha3
  ☆81Updated last year
• openhwgroup / cv-hpdcache
  RTL sources of the High-Performance L1 Dcache (HPDcache) for OpenHW CV cores
  ☆89Updated this week
• ccelio / chisel-style-guide
  A Style Guide for the Chisel Hardware Construction Language
  ☆108Updated 4 years ago
• pulp-platform / spatz
  Spatz is a compact RISC-V-based vector processor meant for high-performance, small computing clusters.
  ☆114Updated this week