Alternatives and similar repositories for HuanCun:

Users that are interested in HuanCun are comparing it to the libraries listed below

• OpenXiangShan / fudian
  Open source high performance IEEE-754 floating unit
  ☆67Updated last year
• OpenXiangShan / xs-env
  XiangShan Frontend Develop Environment
  ☆54Updated 2 weeks ago
• OpenXiangShan / difftest
  Modern co-simulation framework for RISC-V CPUs
  ☆139Updated this week
• OpenXiangShan / CoupledL2
  Open-source non-blocking L2 cache
  ☆37Updated this week
• ucb-bar / testchipip
  ☆82Updated last month
• chipsalliance / playground
  chipyard in mill :P
  ☆77Updated last year
• zero-day-labs / riscv-iommu
  IOMMU IP compliant with the RISC-V IOMMU Specification v1.0
  ☆86Updated this week
• chipsalliance / rocket-tools
  Software tools that support rocket-chip (GNU toolchain, ISA simulator, tests)
  ☆53Updated last year
• pulp-platform / iDMA
  A modular, parametrizable, and highly flexible Data Movement Accelerator (DMA)
  ☆135Updated last week
• ucb-bar / constellation
  A Chisel RTL generator for network-on-chip interconnects
  ☆184Updated this week
• ucb-bar / hwacha
  Microarchitecture implementation of the decoupled vector-fetch accelerator
  ☆150Updated last year
• riscv-boom / riscv-coremark
  Setup scripts and files needed to compile CoreMark on RISC-V
  ☆64Updated 7 months ago
• cnrv / fpga-rocket-chip
  Wrapper for Rocket-Chip on FPGAs
  ☆129Updated 2 years ago
• ic-lab-duth / RISC-V-Vector
  Vector processor for RISC-V vector ISA
  ☆115Updated 4 years ago
• freechipsproject / chisel-testers
  Provides various testers for chisel users
  ☆100Updated 2 years ago
• ovh / sv2chisel
  (System)Verilog to Chisel translator
  ☆111Updated 2 years ago
• pulp-platform / culsans
  Tightly-coupled cache coherence unit for CVA6 using the ACE protocol
  ☆30Updated 10 months ago
• OpenXiangShan / nexus-am
  ☆33Updated 3 weeks ago
• ucb-ucie / uciedigital
  Pure digital components of a UCIe controller
  ☆55Updated last week
• pulp-platform / spatz
  Spatz is a compact RISC-V-based vector processor meant for high-performance, small computing clusters.
  ☆99Updated this week
• ucb-bar / chiseltest
  The batteries-included testing and formal verification library for Chisel-based RTL designs.
  ☆231Updated 6 months ago
• chipsalliance / riscv-vector-tests
  Unit tests generator for RVV 1.0
  ☆78Updated this week
• IntelLabs / riscv-vector
  Vector Acceleration IP core for RISC-V*
  ☆170Updated this week
• carlosedp / chiselv
  A RISC-V Core (RV32I) written in Chisel HDL
  ☆102Updated 9 months ago
• OpenXiangShan / YunSuan
  This repo includes XiangShan's function units
  ☆18Updated last week
• ucb-bar / sha3
  ☆78Updated last year
• pulp-platform / pulp_cluster
  The multi-core cluster of a PULP system.
  ☆80Updated this week
• sycuricon / starship
  Run rocket-chip on FPGA
  ☆65Updated 4 months ago
• OSCPU / chisel-playground
  ☆63Updated last month
• pulp-platform / pulp_soc
  pulp_soc is the core building component of PULP based SoCs
  ☆79Updated this week