Documentation for XiangShan
☆435Apr 29, 2026Updated last week
Alternatives and similar repositories for XiangShan-doc
Users that are interested in XiangShan-doc are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- Open-source high-performance RISC-V processor☆6,996Updated this week
- Open-source high-performance non-blocking cache☆95Apr 16, 2026Updated 3 weeks ago
- XiangShan Frontend Develop Environment☆71Apr 30, 2026Updated last week
- Modern co-simulation framework for RISC-V CPUs☆174Updated this week
- ☆141Updated this week
- 1-Click AI Models by DigitalOcean Gradient • AdDeploy popular AI models on DigitalOcean Gradient GPU virtual machines with just a single click. Zero configuration with optimized deployments.
- RISC-V SoC designed by students in UCAS☆1,525Apr 28, 2026Updated last week
- This repo includes XiangShan's function units☆30Apr 15, 2026Updated 3 weeks ago
- Super fast RISC-V ISA emulator for XiangShan processor☆328Updated this week
- Open-source non-blocking L2 cache☆60Updated this week
- OpenXuantie - OpenC910 Core☆1,430Jun 28, 2024Updated last year
- SonicBOOM: The Berkeley Out-of-Order Machine☆2,148Mar 11, 2026Updated last month
- ☆43Apr 17, 2026Updated 2 weeks ago
- GPGPU processor supporting RISCV-V extension, developed with Chisel HDL☆896Updated this week
- 一生一芯的信息发布和内容网站☆136Nov 21, 2023Updated 2 years ago
- GPUs on demand by Runpod - Special Offer Available • AdRun AI, ML, and HPC workloads on powerful cloud GPUs—without limits or wasted spend. Deploy GPUs in under a minute and pay by the second.
- 体系结构研讨 + ysyx高阶大纲 (WIP☆209Oct 14, 2024Updated last year
- An Agile RISC-V SoC Design Framework with in-order cores, out-of-order cores, accelerators, and more☆2,241Apr 29, 2026Updated last week
- Scripts for XiangShan☆17Apr 30, 2026Updated last week
- Digital Design with Chisel☆914Updated this week
- Rocket Chip Generator☆3,757Apr 21, 2026Updated 2 weeks ago
- (WIP) A relatively simple pipelined RISC-V core, written in Bluespec SystemVerilog☆12Sep 9, 2021Updated 4 years ago
- Documentation for XiangShan Design☆49Apr 30, 2026Updated last week
- 第一届 RISC-V 中国峰会的幻灯片等资料存放☆38Nov 17, 2022Updated 3 years ago
- ☆67Aug 5, 2024Updated last year
- Deploy to Railway using AI coding agents - Free Credits Offer • AdUse Claude Code, Codex, OpenCode, and more. Autonomous software development now has the infrastructure to match with Railway.
- Chisel: A Modern Hardware Design Language☆4,650Updated this week
- A RISC-V core running Debian (and a LoongArch core running Linux).☆23Nov 24, 2025Updated 5 months ago
- Spike, a RISC-V ISA Simulator☆3,083Apr 29, 2026Updated last week
- Generator Bootcamp Material: Learn Chisel the Right Way☆1,130Sep 10, 2024Updated last year
- ☆1,996Apr 29, 2026Updated last week
- Instruction Set Generator initially contributed by Futurewei☆308Oct 17, 2023Updated 2 years ago
- Ocelot: The Berkeley Out-of-Order Machine With V-EXT support☆247Jan 14, 2026Updated 3 months ago
- The PULP Ara is a 64-bit Vector Unit, compatible with the RISC-V Vector Extension Version 1.0, working as a coprocessor to CORE-V's CVA6 …☆515Apr 24, 2026Updated last week
- Crowdsourced Verification Project (UnityChip Verification) for the Xiangshan Processor☆48Apr 3, 2026Updated last month
- AI Agents on DigitalOcean Gradient AI Platform • AdBuild production-ready AI agents using customizable tools or access multiple LLMs through a single endpoint. Create custom knowledge bases or connect external data.
- Open source high performance IEEE-754 floating unit☆94Feb 26, 2024Updated 2 years ago
- 关于RISC-V你所需要知道的一切☆560Apr 1, 2023Updated 3 years ago
- Functional verification project for the CORE-V family of RISC-V cores.☆677Apr 16, 2026Updated 2 weeks ago
- ☆231Jun 25, 2025Updated 10 months ago
- A template project for beginning new Chisel work☆696Feb 24, 2026Updated 2 months ago
- Random instruction generator for RISC-V processor verification☆1,291Apr 3, 2026Updated last month
- A RISC-V ELF psABI Document☆844Apr 25, 2026Updated last week