OpenXiangShan / XiangShan-docLinks
Documentation for XiangShan
☆415Updated this week
Alternatives and similar repositories for XiangShan-doc
Users that are interested in XiangShan-doc are comparing it to the libraries listed below
Sorting:
- GPGPU processor supporting RISCV-V extension, developed with Chisel HDL☆743Updated this week
- Simple RISC-V 3-stage Pipeline in Chisel☆577Updated 9 months ago
- OpenXuantie - OpenC910 Core☆1,274Updated 11 months ago
- Digital Design with Chisel☆837Updated 3 weeks ago
- ☆122Updated 2 years ago
- The PULP Ara is a 64-bit Vector Unit, compatible with the RISC-V Vector Extension Version 1.0, working as a coprocessor to CORE-V's CVA6 …☆429Updated last week
- 关于RISC-V你所需要知道的一切☆561Updated 2 years ago
- ☆277Updated this week
- chisel tutorial exercises and answers☆728Updated 3 years ago
- Generator Bootcamp Material: Learn Chisel the Right Way☆1,036Updated 8 months ago
- educational microarchitectures for risc-v isa☆714Updated 2 months ago
- A template project for beginning new Chisel work☆639Updated last week
- 32-bit Superscalar RISC-V CPU☆1,024Updated 3 years ago
- The Ultra-Low Power RISC-V Core☆1,508Updated 7 months ago
- ☆190Updated last month
- VeeR EH1 core☆878Updated 2 years ago
- Instruction Set Generator initially contributed by Futurewei☆282Updated last year
- Lab exercises for Chisel in the digital electronics 2 course at DTU☆198Updated 2 months ago
- Random instruction generator for RISC-V processor verification☆1,126Updated 3 months ago
- OpenXuantie - OpenC906 Core☆354Updated 11 months ago
- This is the top-level project for the PULP Platform. It instantiates a PULP open-source system with a PULP SoC (microcontroller) domain a…☆493Updated 6 months ago
- RISC-V Cores, SoC platforms and SoCs☆881Updated 4 years ago
- CV32E40P is an in-order 4-stage RISC-V RV32IMFCXpulp CPU based on RI5CY from PULP-Platform☆1,077Updated last week
- AXI SystemVerilog synthesizable IP modules and verification infrastructure for high-performance on-chip communication☆1,286Updated last week
- 为推广RISC-V尽些薄力☆311Updated last year
- 体系结构研讨 + ysyx高阶大纲 (WIP☆162Updated 7 months ago
- ☆158Updated last month
- Functional verification project for the CORE-V family of RISC-V cores.☆545Updated last week
- Chisel examples and code snippets☆251Updated 2 years ago
- OpenSource HummingBird RISC-V Software Development Kit☆157Updated last year