Documentation for XiangShan
☆445Aug 10, 2026Updated this week
Alternatives and similar repositories for XiangShan-doc
Users that are interested in XiangShan-doc are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- Open-source high-performance RISC-V processor☆7,192Updated this week
- Open-source high-performance non-blocking cache☆100Jun 17, 2026Updated last month
- XiangShan Frontend Develop Environment☆72Aug 7, 2026Updated last week
- Modern co-simulation framework for RISC-V CPUs☆182Updated this week
- ☆151Updated this week
- Wordpress hosting with auto-scaling - Free Trial Offer • AdFully Managed hosting for WordPress and WooCommerce businesses that need reliable, auto-scalable performance. Cloudways SafeUpdates now available.
- RISC-V SoC designed by students in UCAS☆1,544Jun 5, 2026Updated 2 months ago
- This repo includes XiangShan's function units☆32Updated this week
- Super fast RISC-V ISA emulator for XiangShan processor☆340Updated this week
- Documentation for XiangShan Design☆50Jul 12, 2026Updated last month
- OpenXuantie - OpenC910 Core☆1,463Jun 28, 2024Updated 2 years ago
- Open-source non-blocking L2 cache☆65Updated this week
- ☆44Aug 7, 2026Updated last week
- 一生一芯的信息发布和内容网站☆138Nov 21, 2023Updated 2 years ago
- SonicBOOM: The Berkeley Out-of-Order Machine☆2,217Updated this week
- Managed hosting for WordPress and PHP on Cloudways • AdManaged hosting for WordPress, Magento, Laravel, or PHP apps, on multiple cloud providers. Deploy in minutes on Cloudways by DigitalOcean.
- Scripts for XiangShan☆18Updated this week
- GPGPU processor supporting RISCV-V extension, developed with Chisel HDL☆938Updated this week
- 体系结构研讨 + ysyx高阶大纲 (WIP☆218Oct 14, 2024Updated last year
- An Agile RISC-V SoC Design Framework with in-order cores, out-of-order cores, accelerators, and more☆2,355Updated this week
- 第一届 RISC-V 中国峰会的幻灯片等资料存放☆38Nov 17, 2022Updated 3 years ago
- Rocket Chip Generator☆3,845Jun 2, 2026Updated 2 months ago
- Digital Design with Chisel☆926Jul 21, 2026Updated 3 weeks ago
- ☆85Jun 1, 2022Updated 4 years ago
- (WIP) A relatively simple pipelined RISC-V core, written in Bluespec SystemVerilog☆12Sep 9, 2021Updated 4 years ago
- Managed Kubernetes at scale on DigitalOcean • AdDigitalOcean Kubernetes includes the control plane, bandwidth allowance, container registry, automatic updates, and more for free.
- ☆67Aug 5, 2024Updated 2 years ago
- Chisel: A Modern Hardware Design Language☆4,759Updated this week
- A RISC-V core running Debian (and a LoongArch core running Linux).☆23Nov 24, 2025Updated 8 months ago
- Spike, a RISC-V ISA Simulator☆3,197Updated this week
- Generator Bootcamp Material: Learn Chisel the Right Way☆1,149Sep 10, 2024Updated last year
- ☆17Updated this week
- The User Guide of XiangShan.☆21Jun 1, 2026Updated 2 months ago
- ☆2,208Updated this week
- Instruction Set Generator initially contributed by Futurewei☆312Oct 17, 2023Updated 2 years ago
- GPU virtual machines on DigitalOcean Gradient AI • AdGet to production fast with high-performance AMD and NVIDIA GPUs you can spin up in seconds. The definition of operational simplicity.
- The PULP Ara is a 64-bit Vector Unit, compatible with the RISC-V Vector Extension Version 1.0, working as a coprocessor to CORE-V's CVA6 …☆537Updated this week
- Open source high performance IEEE-754 floating unit☆99Feb 26, 2024Updated 2 years ago
- Crowdsourced Verification Project (UnityChip Verification) for the Xiangshan Processor☆50May 12, 2026Updated 3 months ago
- Ocelot: The Berkeley Out-of-Order Machine With V-EXT support☆261Updated this week
- 关于RISC-V你所需要知道的一切☆566Apr 1, 2023Updated 3 years ago
- Functional verification project for the CORE-V family of RISC-V cores.☆709Updated this week
- ☆243Jun 25, 2025Updated last year