Alternatives and similar repositories for m1-pmu-gen:

Users that are interested in m1-pmu-gen are comparing it to the libraries listed below

• jiegec / apple-pmu
  Dump Apple PMU counter definitions from `/usr/share/kpep` in macOS
  ☆13Updated 2 weeks ago
• jiegec / cpu
  Microarchitecture diagrams of several CPUs
  ☆31Updated 3 weeks ago
• jiegec / chisel-memory-lower
  Lower chisel memories to SRAM macros
  ☆12Updated last year
• jiegec / verilog-lang
  A hand-written recursive decent Verilog parser.
  ☆11Updated 2 years ago
• chipsalliance / chisel-interface
  The 'missing header' for Chisel
  ☆19Updated last month
• jiegec / fpu-wrappers
  Wrappers for open source FPU hardware implementations.
  ☆31Updated last year
• dramforever / opensbi-h
  WIP: A fork of OpenSBI, with software-emulated hypervisor extension support
  ☆38Updated last month
• comparch-security / FlexiCAS
  A Flexible Cache Architectural Simulator
  ☆14Updated 4 months ago
• circt / arc-tests
  A collection of tests and benchmarks for the Arc simulation backend of CIRCT
  ☆28Updated 2 months ago
• iscas-tis / riscv-spec-core
  Minimal RISC-V Chisel design strictly reflecting the ISA document for verification.
  ☆13Updated this week
• pku-liang / Cement
  The Next-gen Language & Compiler Powering Efficient Hardware Design
  ☆27Updated 3 months ago
• CircuitCoder / ld.meow.so
  Toy ELF dynlinker & interp
  ☆10Updated 10 months ago
• sequencer / zaozi
  A eDSL framework based on Scala and MLIR, focusing on the Hardware design.
  ☆32Updated this week
• OpenXiangShan / xfuzz
  Fuzzing General-Purpose Hardware Designs with Software Fuzzers
  ☆16Updated last month
• CircuitCoder / ChannelOS
  What if everything is a io_uring?
  ☆16Updated 2 years ago
• chipsalliance / rocket-chip-fpga-shells
  Wrapper shells enabling designs generated by rocket-chip to map onto certain FPGA boards
  ☆18Updated 4 months ago
• jiegec / rvv-kernels
  Implements kernels with RISC-V Vector
  ☆22Updated 2 years ago
• jiegec / cpu-micro-benchmarks
  CPU micro benchmarks
  ☆55Updated 2 weeks ago
• jiegec / SPECCPU2017Harmony
  Run SPEC CPU 2017 benchmark on OpenHarmony/HarmonyOS NEXT
  ☆13Updated 2 months ago
• chipsalliance / chisel-nix
  Nix template for the chisel-based industrial designing flows.
  ☆41Updated this week
• ljwljwljwljw / DiplomaticBackend
  ☆17Updated 3 years ago
• RISMicroDevices / CHIron
  Open-source AMBA CHI infrastructures (supporting Issue B, E.b)
  ☆18Updated this week
• jiegec / rocket-chip-vcu128
  Run Rocket Chip on VCU128
  ☆30Updated 4 months ago
• riscv / riscv-control-transfer-records
  This repo contains a RISC-V ISA extension (proposal) to allow recording of control transfer history to on-chip registers, to support usag…
  ☆20Updated 2 months ago
• OSCPU / openperf
  ☆11Updated 2 months ago
• dramforever / ixayoi
  (WIP) A relatively simple pipelined RISC-V core, written in Bluespec SystemVerilog
  ☆12Updated 3 years ago
• junjie1475 / MacOS_CoreBinder
  Kernel Extension allows to pin thread on a certain cpu core on Apple Silicon machines
  ☆17Updated 5 months ago
• inclyc / talk-simd-llvm
  Talk about how to add new SIMD extension support, in llvm backend (zh_CN)
  ☆7Updated 4 months ago
• Oyami-Srk / RISCV-GDB-Paging
  Paging Debug tool for GDB using python
  ☆13Updated 2 years ago
• OpenXiangShan / CoupledL2
  Open-source non-blocking L2 cache
  ☆40Updated this week