Alternatives and similar repositories for env-scripts

Users that are interested in env-scripts are comparing it to the libraries listed below

• merledu / TileLink
  TileLink Uncached Lightweight (TL-UL) implementation on Chisel.
  ☆20Updated 4 years ago
• whutddk / RiftCore
  RiftCore is a 9-stage, single-issue, out-of-order 64-bits RISC-V Core, which supports RV64IMC and 3-level Cache System
  ☆42Updated 2 years ago
• Xilinx / pcie-model
  PCI Express controller model
  ☆57Updated 2 years ago
• ic-lab-duth / DRIM-S
  DUTH RISC-V Superscalar Microprocessor
  ☆31Updated 8 months ago
• 0ctobyte / procyon
  Procyon is the brightest star in the constellation of Canis Minor. But it's also the name of my RISC-V out-of-order processor.
  ☆12Updated 2 years ago
• pulp-platform / axi_llc
  ☆30Updated 2 months ago
• sequencer / arithmetic
  ☆33Updated 3 months ago
• RPG-7 / HGA101_GPU
  ☆16Updated 4 years ago
• OpenXiangShan / YunSuan
  This repo includes XiangShan's function units
  ☆26Updated 3 weeks ago
• ucb-bar / block-inclusivecache-sifive
  ☆12Updated 3 years ago
• PacoReinaCampo / MPSoC-NoC
  Network on Chip for MPSoC
  ☆26Updated last month
• ucb-bar / nvdla-wrapper
  Wraps the NVDLA project for Chipyard integration
  ☆21Updated 2 months ago
• himanshu5-prog / vortexGPU
  ☆21Updated 4 years ago
• pulp-platform / redundancy_cells
  SystemVerilog IPs and Modules for architectural redundancy designs.
  ☆14Updated last week
• AlessandroCilardo / NaplesPU
  The official NaplesPU hardware code repository
  ☆16Updated 5 years ago
• riscv-verification / riscvISACOV
  SystemVerilog Functional Coverage for RISC-V ISA
  ☆28Updated 3 weeks ago
• esa-tu-darmstadt / tapasco-riscv
  RISC-V soft-core PEs for TaPaSCo
  ☆21Updated last year
• adki / cosim_bfm_library
  HW-SW Co-Simulation Library for AMBA AXI BFM using DPI/VPI
  ☆32Updated 6 months ago
• pulp-platform / apb
  APB Logic
  ☆18Updated 6 months ago
• bhunt2 / DDR4Sim
  DDR4 Simulation Project in System Verilog
  ☆41Updated 10 years ago
• ucb-bar / esp-isa-sim
  Custom extensions to the RISC-V isa simulator for the UCB-BAR ESP project
  ☆17Updated 2 years ago
• RoaLogic / plic
  Platform Level Interrupt Controller
  ☆41Updated last year
• whutddk / Rift2Core
  Based on Chisel3, Rift2Core is a 9-stage, out-of-order, 64-bits RISC-V Core, which supports RV64GC.
  ☆40Updated last year
• alexforencich / dma-bench
  ☆27Updated 3 years ago
• openhwgroup / cv32e41p
  4 stage, in-order, secure RISC-V core based on the CV32E40P with Zfinx and Zce ISA extentions
  ☆27Updated last year
• nju-mips / noop-lo
  A simple OoO processor developed by njuallen and wierton, it won 2nd prize in LoongsonCup18.
  ☆28Updated 5 years ago
• SeanZarzycki / openSPARC-FPU
  ASIC Design of the openSPARC Floating Point Unit
  ☆13Updated 8 years ago
• chipsalliance / systemc-compiler
  Intel Compiler for SystemC
  ☆23Updated 2 years ago
• RSPwFPGAs / qemu-hdl-cosim
  VM-HDL Co-Simulation for Servers with PCIe-Connected FPGAs
  ☆47Updated 4 years ago
• OpenXiangShan / nexus-am
  ☆35Updated last month