Alternatives and similar repositories for XS-Verilog-Library

Users that are interested in XS-Verilog-Library are comparing it to the libraries listed below

• RV-BOSC / OpenNoC
  ☆198Updated 4 months ago
• dpretet / axi-crossbar
  An AXI4 crossbar implementation in SystemVerilog
  ☆176Updated last month
• hyf6661669 / verilog_library
  HYF's high quality verilog codes
  ☆15Updated 10 months ago
• kaitoukito / Integrated-Circuit-Textbooks
  Collect some IC textbooks for learning.
  ☆167Updated 3 years ago
• pulp-platform / fpu
  ☆56Updated 6 years ago
• adki / gen_amba
  AMBA bus generator including AXI, AHB, and APB
  ☆107Updated 4 years ago
• THU-DSP-LAB / ventus-gpgpu-verilog
  GPGPU supporting RISCV-V, developed with verilog HDL
  ☆116Updated 8 months ago
• Verdvana / AXI4_Interconnect
  AXI总线连接器
  ☆104Updated 5 years ago
• OSCPU / ysyxSoC
  ☆88Updated 3 weeks ago
• pulp-platform / FlooNoC
  A Fast, Low-Overhead On-chip Network
  ☆231Updated last week
• amonemi / ProNoC
  Prototype-network-on-chip (ProNoC) is an EDA tool that facilitates prototyping of custom heterogeneous NoC-based many-core-SoC (MCSoC).
  ☆59Updated last week
• ic-lab-duth / RISC-V-Vector
  Vector processor for RISC-V vector ISA
  ☆129Updated 5 years ago
• xiaoerlang0359 / E203plus
  upgrade to e203 (a risc-v core)
  ☆45Updated 5 years ago
• ForrestBlue / cortexm0ds
  ☆69Updated 9 years ago
• mmxsrup / axi4-interface
  AXI4 and AXI4-Lite interface definitions
  ☆96Updated 5 years ago
• taichi-ishitani / tnoc
  Network on Chip Implementation written in SytemVerilog
  ☆192Updated 3 years ago
• freecores / dma_axi
  AXI DMA 32 / 64 bits
  ☆121Updated 11 years ago
• lizhirui / AXI_spec_chinese
  AXI协议规范中文翻译版
  ☆164Updated 3 years ago
• agalimberti / NoCRouter
  RTL Network-on-Chip Router Design in SystemVerilog by Andrea Galimberti, Filippo Testa and Alberto Zeni
  ☆131Updated 7 years ago
• hyf6661669 / Synopsys-Documents
  Some useful documents of Synopsys
  ☆88Updated 3 years ago
• WilsonChen003 / HDLGen
  HDLGen is an HDL generation tool, supporting embedded Perl or Python script, reduce manual work & improve effiency with a few embedded f…
  ☆106Updated last year
• risclite / SuperScalar-RISCV-CPU
  SSRV(Super-Scalar RISC-V) --- Super-scalar out-of-order RV32IMC CPU core, 6.4 CoreMark/MHz.
  ☆217Updated 5 years ago
• jasonlin316 / RISC-V-CPU
  A RISC-V 5-stage pipelined CPU that supports vector instructions. Tape-out with U18 technology.
  ☆136Updated 5 years ago
• erihsu / INT_FP_MAC
  INT8 & FP16 multiplier accumulator (MAC) design with UVM verification completed.
  ☆105Updated 5 years ago
• bakhshalipour / NoC-Verilog
  A verilog implementation for Network-on-Chip
  ☆77Updated 7 years ago
• abdelrhman-oun / DDR5_PHY_WriteOperation
  ☆64Updated 3 years ago
• shawn110285 / Cookabarra
  a training-target implementation of rv32im, designed to be simple and easy to understand
  ☆61Updated 3 years ago
• kuladeepsaireddy / OpenNoc
  ☆37Updated 6 years ago
• nishthaparashar / Floating-Point-ALU-in-Verilog
  32-Bit Algorithms of Floating Point Operations are implemented on Verilog with logic Operations.
  ☆92Updated 6 years ago
• OSCPU / yosys-sta
  ☆83Updated 6 months ago