☆47May 11, 2022Updated 3 years ago
Alternatives and similar repositories for XS-Verilog-Library
Users that are interested in XS-Verilog-Library are comparing it to the libraries listed below
Sorting:
- HYF's high quality verilog codes☆16Dec 25, 2024Updated last year
- Basic floating-point components for RISC-V processors☆11Aug 13, 2017Updated 8 years ago
- 6-stage dual-issue in-order superscalar risc-v cpu with floating point unit☆14Updated this week
- ☆14Feb 24, 2025Updated last year
- Open source high performance IEEE-754 floating unit☆90Feb 26, 2024Updated 2 years ago
- This repo includes XiangShan's function units☆30Feb 14, 2026Updated 2 weeks ago
- Scripts for XiangShan☆17Updated this week
- For CPU experiment☆14Feb 23, 2021Updated 5 years ago
- JTAG DPI module for OpenRISC simulation with Verilator☆17Oct 27, 2012Updated 13 years ago
- The UVM written in Python☆17Dec 26, 2025Updated 2 months ago
- ☆78Feb 2, 2026Updated last month
- verification of simple axi-based cache☆18May 14, 2019Updated 6 years ago
- 一些小的工程记录☆25Feb 2, 2020Updated 6 years ago
- RiftCore is a 9-stage, single-issue, out-of-order 64-bits RISC-V Core, which supports RV64IMC and 3-level Cache System☆45Sep 21, 2022Updated 3 years ago
- [UNRELEASED] FP div/sqrt unit for transprecision☆26Sep 9, 2025Updated 5 months ago
- a 2048 bit RSA verilog project basing on Montgomery , Karatsuba multiplier☆25Mar 11, 2022Updated 3 years ago
- amba3 apb/axi vip☆53Feb 24, 2015Updated 11 years ago
- ☆58Feb 18, 2019Updated 7 years ago
- Designing CNN accelerator using a Xilinx FPGA board and comparing performance with CPU.☆21Feb 28, 2021Updated 5 years ago
- soc integration script and integration smoke script☆24Sep 12, 2022Updated 3 years ago
- 《关于浮点运算：作为程序员都应该了解什么？》☆27Apr 17, 2018Updated 7 years ago
- ☆11May 31, 2016Updated 9 years ago
- TCP/IP controlled VPI JTAG Interface.☆69Jan 16, 2025Updated last year
- Verification IP for APB protocol☆33Sep 9, 2020Updated 5 years ago
- Project aimed at implementing floating point operators using the DSP48E1 slice.☆30Mar 29, 2013Updated 12 years ago
- Functional Verification of Physical Layer of PCI Express Gen5.0 Graduation Project Using UVM☆25Jul 17, 2025Updated 7 months ago
- Toy RISC-V LLVM backend☆30Aug 15, 2022Updated 3 years ago
- TEMPORARY FORK of the riscv-compliance repository☆32Mar 31, 2021Updated 4 years ago
- Wrappers for open source FPU hardware implementations.☆37Nov 27, 2025Updated 3 months ago
- 多核处理器 ;ring network , four core, shared space memory ,directory-based cache coherency☆26Aug 28, 2016Updated 9 years ago
- DDR3 SDRAM Memory Controller Design & Synthesis using System Verilog☆32Nov 6, 2018Updated 7 years ago
- 计算机体系结构Project1,用Python实现一个MipsSimulator（如果你上CMS的课还是退课吧）☆27Dec 6, 2017Updated 8 years ago
- A RISC-V simulator implementing RV32G[C].☆35Feb 3, 2023Updated 3 years ago
- Cluster-level matrix unit integration into GPUs, implemented in Chipyard SoC☆49Jan 20, 2026Updated last month
- RISC-V Configuration Validator☆82Mar 28, 2025Updated 11 months ago
- UVM APB VIP, part of AMBA3&AMBA4 feature supported☆34Aug 24, 2020Updated 5 years ago
- ☆22Jun 4, 2025Updated 9 months ago
- a scaleable ring topology network on chip (NoC) implemented in BSV☆12Oct 14, 2014Updated 11 years ago
- Modular Multi-ported SRAM-based Memory☆31Nov 8, 2024Updated last year