OpenXiangShan / XS-Verilog-Library
☆41Updated 2 years ago
Alternatives and similar repositories for XS-Verilog-Library:
Users that are interested in XS-Verilog-Library are comparing it to the libraries listed below
- An AXI4 crossbar implementation in SystemVerilog☆145Updated this week
- ☆152Updated last week
- ☆86Updated this week
- INT8 & FP16 multiplier accumulator (MAC) design with UVM verification completed.☆99Updated 4 years ago
- AXI DMA 32 / 64 bits☆112Updated 10 years ago
- HDLGen is an HDL generation tool, supporting embedded Perl or Python script, reduce manual work & improve effiency with a few embedded f…☆96Updated last year
- AXI总线连接器☆97Updated 5 years ago
- a training-target implementation of rv32im, designed to be simple and easy to understand☆58Updated 3 years ago
- AXI4 and AXI4-Lite interface definitions☆92Updated 4 years ago
- GPGPU supporting RISCV-V, developed with verilog HDL☆96Updated 2 months ago
- A verilog implementation for Network-on-Chip☆73Updated 7 years ago
- Vector processor for RISC-V vector ISA☆117Updated 4 years ago
- Some useful documents of Synopsys☆72Updated 3 years ago
- ☆64Updated 2 years ago
- 3×3脉动阵列乘法器☆44Updated 5 years ago
- FFT generator using Chisel☆59Updated 3 years ago
- some knowleage about SystemC/TLM etc.☆24Updated last year
- upgrade to e203 (a risc-v core)☆43Updated 4 years ago
- AMBA bus generator including AXI, AHB, and APB☆100Updated 3 years ago
- A Fast, Low-Overhead On-chip Network☆200Updated last week
- HDL code for a DDR4 memory controller implementing an Open Page Policy and Out of Order execution.☆74Updated 7 years ago
- ☆46Updated 6 years ago
- HYF's high quality verilog codes☆12Updated 4 months ago
- The Ultra-Low Power RISC Core☆15Updated 5 years ago
- AXI master to AHB slave, support INCR/WRAP, out of standing, do not advanced feature such as support out of order, retry, split, etc☆39Updated 3 years ago
- ☆32Updated 6 years ago
- A 16-bit by 16-bit signed binary multiplier based on the Radix-4 Booth algorithm and Wallace Tree reduction☆48Updated 8 months ago
- ☆62Updated 9 years ago
- A generic implementation of AMBA AXI4 communication protocol. The design provides a master, a slave and an interconnect with multiple mas…☆38Updated 2 years ago
- AXI协议规范中文翻译版☆146Updated 2 years ago