Alternatives and similar repositories for XS-Verilog-Library

Users that are interested in XS-Verilog-Library are comparing it to the libraries listed below

• RV-BOSC / OpenNoC
  ☆190Updated 2 months ago
• hyf6661669 / verilog_library
  HYF's high quality verilog codes
  ☆15Updated 8 months ago
• dpretet / axi-crossbar
  An AXI4 crossbar implementation in SystemVerilog
  ☆174Updated last week
• kaitoukito / Integrated-Circuit-Textbooks
  Collect some IC textbooks for learning.
  ☆163Updated 3 years ago
• xiaoerlang0359 / E203plus
  upgrade to e203 (a risc-v core)
  ☆44Updated 5 years ago
• ic-lab-duth / RISC-V-Vector
  Vector processor for RISC-V vector ISA
  ☆126Updated 4 years ago
• THU-DSP-LAB / ventus-gpgpu-verilog
  GPGPU supporting RISCV-V, developed with verilog HDL
  ☆110Updated 6 months ago
• pulp-platform / fpu
  ☆53Updated 6 years ago
• freecores / dma_axi
  AXI DMA 32 / 64 bits
  ☆120Updated 11 years ago
• wuzeyou / Multiplier16X16
  Classic Booth Code, Wallace Tree, and SquareRoot Carry Select Adder
  ☆119Updated 12 years ago
• OSCPU / ysyxSoC
  ☆86Updated this week
• WilsonChen003 / HDLGen
  HDLGen is an HDL generation tool, supporting embedded Perl or Python script, reduce manual work & improve effiency with a few embedded f…
  ☆104Updated last year
• Verdvana / AXI4_Interconnect
  AXI总线连接器
  ☆103Updated 5 years ago
• erihsu / INT_FP_MAC
  INT8 & FP16 multiplier accumulator (MAC) design with UVM verification completed.
  ☆104Updated 4 years ago
• ForrestBlue / cortexm0ds
  ☆68Updated 9 years ago
• ananthbhat94 / DDR4MemoryController
  HDL code for a DDR4 memory controller implementing an Open Page Policy and Out of Order execution.
  ☆79Updated 7 years ago
• lizhirui / AXI_spec_chinese
  AXI协议规范中文翻译版
  ☆163Updated 3 years ago
• adki / gen_amba
  AMBA bus generator including AXI, AHB, and APB
  ☆106Updated 4 years ago
• devindang / openip-hdl
  Open IP in Hardware Description Language.
  ☆25Updated 2 years ago
• kuladeepsaireddy / OpenNoc
  ☆35Updated 6 years ago
• pulp-platform / FlooNoC
  A Fast, Low-Overhead On-chip Network
  ☆224Updated last month
• taichi-ishitani / tnoc
  Network on Chip Implementation written in SytemVerilog
  ☆191Updated 3 years ago
• schoeberl / chisel-lab
  Lab exercises for Chisel in the digital electronics 2 course at DTU
  ☆207Updated 3 months ago
• bakhshalipour / NoC-Verilog
  A verilog implementation for Network-on-Chip
  ☆76Updated 7 years ago
• abdelrhman-oun / DDR5_PHY_WriteOperation
  ☆62Updated 3 years ago
• zhangzek / 3x3_matrix_Systolic_Array_multiplier
  3×3脉动阵列乘法器
  ☆47Updated 5 years ago
• lauchinyuan / Booth4_wallace_MULT16_16
  A 16-bit by 16-bit signed binary multiplier based on the Radix-4 Booth algorithm and Wallace Tree reduction
  ☆56Updated last year
• agalimberti / NoCRouter
  RTL Network-on-Chip Router Design in SystemVerilog by Andrea Galimberti, Filippo Testa and Alberto Zeni
  ☆129Updated 7 years ago
• amonemi / ProNoC
  Prototype-network-on-chip (ProNoC) is an EDA tool that facilitates prototyping of custom heterogeneous NoC-based many-core-SoC (MCSoC).
  ☆59Updated last month
• mmxsrup / axi4-interface
  AXI4 and AXI4-Lite interface definitions
  ☆94Updated 4 years ago