OpenXiangShan / XS-Verilog-LibraryLinks
☆43Updated 3 years ago
Alternatives and similar repositories for XS-Verilog-Library
Users that are interested in XS-Verilog-Library are comparing it to the libraries listed below
Sorting:
- ☆176Updated last month
- An AXI4 crossbar implementation in SystemVerilog☆164Updated last month
- AXI DMA 32 / 64 bits☆116Updated 11 years ago
- HYF's high quality verilog codes☆14Updated 7 months ago
- ☆52Updated 6 years ago
- A Fast, Low-Overhead On-chip Network☆220Updated this week
- a training-target implementation of rv32im, designed to be simple and easy to understand☆60Updated 3 years ago
- Vector processor for RISC-V vector ISA☆122Updated 4 years ago
- GPGPU supporting RISCV-V, developed with verilog HDL☆104Updated 5 months ago
- upgrade to e203 (a risc-v core)☆44Updated 4 years ago
- Lab exercises for Chisel in the digital electronics 2 course at DTU☆205Updated 2 months ago
- INT8 & FP16 multiplier accumulator (MAC) design with UVM verification completed.☆103Updated 4 years ago
- Collect some IC textbooks for learning.☆150Updated 2 years ago
- HDLGen is an HDL generation tool, supporting embedded Perl or Python script, reduce manual work & improve effiency with a few embedded f…☆102Updated last year
- Some useful documents of Synopsys☆77Updated 3 years ago
- AXI协议规范中文翻译版☆159Updated 3 years ago
- ☆86Updated 3 months ago
- AMBA bus generator including AXI, AHB, and APB☆105Updated 4 years ago
- Network on Chip Implementation written in SytemVerilog☆186Updated 2 years ago
- AXI总线连接器☆102Updated 5 years ago
- 3×3脉动阵列乘法器☆46Updated 5 years ago
- A Chisel RTL generator for network-on-chip interconnects☆207Updated 2 months ago
- Classic Booth Code, Wallace Tree, and SquareRoot Carry Select Adder☆117Updated 12 years ago
- SSRV(Super-Scalar RISC-V) --- Super-scalar out-of-order RV32IMC CPU core, 6.4 CoreMark/MHz.☆218Updated 4 years ago
- A RISC-V 5-stage pipelined CPU that supports vector instructions. Tape-out with U18 technology.☆132Updated 5 years ago
- ☆67Updated 9 years ago
- ☆34Updated 6 years ago
- Various caches written in Verilog-HDL☆125Updated 10 years ago
- AXI4 and AXI4-Lite interface definitions☆94Updated 4 years ago
- HDL code for a DDR4 memory controller implementing an Open Page Policy and Out of Order execution.☆79Updated 7 years ago