OpenXiangShan / XS-Verilog-Library

Related projects ⓘ

Alternatives and complementary repositories for XS-Verilog-Library

• RV-BOSC / OpenNoC
  ☆61Updated 2 months ago
• xiaoerlang0359 / E203plus
  upgrade to e203 (a risc-v core)
  ☆37Updated 4 years ago
• dpretet / axi-crossbar
  An AXI4 crossbar implementation in SystemVerilog
  ☆121Updated 5 months ago
• lizhirui / DreamCore
  ☆63Updated 2 years ago
• Verdvana / AXI4_Interconnect
  AXI总线连接器
  ☆90Updated 4 years ago
• freecores / dma_axi
  AXI DMA 32 / 64 bits
  ☆97Updated 10 years ago
• erihsu / INT_FP_MAC
  INT8 & FP16 multiplier accumulator (MAC) design with UVM verification completed.
  ☆81Updated 4 years ago
• lizhirui / AXI_spec_chinese
  AXI协议规范中文翻译版
  ☆130Updated 2 years ago
• WilsonChen003 / HDLGen
  HDLGen is an HDL generation tool, supporting embedded Perl or Python script, reduce manual work & improve effiency with a few embedded f…
  ☆86Updated last year
• mmxsrup / axi4-interface
  AXI4 and AXI4-Lite interface definitions
  ☆83Updated 4 years ago
• emwzq / example_uvm
  UVM实战随书源码
  ☆42Updated 5 years ago
• IA-C-Lab-Fudan / Chisel-FFT-generator
  FFT generator using Chisel
  ☆56Updated 3 years ago
• hyf6661669 / Synopsys-Documents
  Some useful documents of Synopsys
  ☆46Updated 3 years ago
• OSCPU / ysyxSoC
  ☆76Updated 2 months ago
• kuladeepsaireddy / OpenNoc
  ☆26Updated 5 years ago
• zhangzek / 3x3_matrix_Systolic_Array_multiplier
  3×3脉动阵列乘法器
  ☆34Updated 5 years ago
• peilin-chen / Zhulong-RISCV-CPU
  CPU Design Based on RISCV ISA
  ☆75Updated 4 months ago
• kaitoukito / Integrated-Circuit-Textbooks
  Collect some IC textbooks for learning.
  ☆100Updated 2 years ago
• ananthbhat94 / DDR4MemoryController
  HDL code for a DDR4 memory controller implementing an Open Page Policy and Out of Order execution.
  ☆68Updated 6 years ago
• shawn110285 / Cookabarra
  a training-target implementation of rv32im, designed to be simple and easy to understand
  ☆54Updated 2 years ago
• siyueyinghua / UVMInPracticesByZhangQiang
  《UVM实战》书本源代码和UVM 1.1d源码及Doc
  ☆31Updated 3 years ago
• hyf6661669 / verilog_library
  HYF's high quality verilog codes
  ☆9Updated last week
• yian521 / OpenC910_Modified
  commit rtl and build cosim env
  ☆13Updated 8 months ago
• adki / gen_amba
  AMBA bus generator including AXI, AHB, and APB
  ☆90Updated 3 years ago
• VenciFreeman / FFT_ChipDesign
  A 16-point radix-4 FFT chip, including Verilog codes, netlists and layout. Group project.
  ☆53Updated 2 months ago
• thuCGRA / SpinalHDL_Chinese_Doc
  Translated SpinalHDL-Doc(v1.7.2) into Chinese
  ☆47Updated last year
• lauchinyuan / Booth4_wallace_MULT16_16
  A 16-bit by 16-bit signed binary multiplier based on the Radix-4 Booth algorithm and Wallace Tree reduction
  ☆30Updated 2 months ago
• devindang / openip-hdl
  Open IP in Hardware Description Language.
  ☆14Updated last year
• Chainsaw-Team / Chainsaw
  a hardware design library based on SpinalHDL, especially for stream processing operators on Xilinx FPGAs for Arithmetic, DSP, Communicati…
  ☆54Updated 10 months ago
• ForrestBlue / cortexm0ds
  ☆51Updated 8 years ago