☆49May 11, 2022Updated 3 years ago
Alternatives and similar repositories for XS-Verilog-Library
Users that are interested in XS-Verilog-Library are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- HYF's high quality verilog codes☆18Dec 25, 2024Updated last year
- This repo includes XiangShan's function units☆30Apr 15, 2026Updated 3 weeks ago
- 6-stage dual-issue in-order superscalar risc-v cpu☆14Updated this week
- JTAG DPI module for OpenRISC simulation with Verilator☆18Oct 27, 2012Updated 13 years ago
- Scripts for XiangShan☆17Updated this week
- Deploy to Railway using AI coding agents - Free Credits Offer • AdUse Claude Code, Codex, OpenCode, and more. Autonomous software development now has the infrastructure to match with Railway.
- a 2048 bit RSA verilog project basing on Montgomery , Karatsuba multiplier☆28Mar 11, 2022Updated 4 years ago
- RiftCore is a 9-stage, single-issue, out-of-order 64-bits RISC-V Core, which supports RV64IMC and 3-level Cache System☆45Sep 21, 2022Updated 3 years ago
- The UVM written in Python☆17Dec 26, 2025Updated 4 months ago
- ☆11Oct 24, 2024Updated last year
- ☆14Feb 24, 2025Updated last year
- Basic floating-point components for RISC-V processors☆12Aug 13, 2017Updated 8 years ago
- Official QEMU mirror. Please see http://wiki.qemu.org/Contribute/SubmitAPatch for how to submit changes to QEMU. Pull Requests are ignore…☆11Mar 5, 2026Updated 2 months ago
- H.264/AVC Baseline Decoder☆16Jul 17, 2014Updated 11 years ago
- For CPU experiment☆14Feb 23, 2021Updated 5 years ago
- Virtual machines for every use case on DigitalOcean • AdGet dependable uptime with 99.99% SLA, simple security tools, and predictable monthly pricing with DigitalOcean's virtual machines, called Droplets.
- A harvard architecture CPU based on RISC-V.☆16Aug 25, 2023Updated 2 years ago
- 4096bit Iterative digit-digit Montgomery Multiplication in Verilog☆19Apr 18, 2022Updated 4 years ago
- R2MDC FFT/IFFT processor adaptive to 64/128/256/512 point☆18Dec 23, 2025Updated 4 months ago
- soc integration script and integration smoke script☆24Sep 12, 2022Updated 3 years ago
- A library to retrieve JEP106 manufacturer strings in Rust.☆11May 7, 2025Updated 11 months ago
- RV64emu is a riscv64 emulator written in rust,can run linux !☆23Oct 5, 2024Updated last year
- Arm Cortex-M0 based Customizable SoC for IoT Applications☆16Nov 4, 2020Updated 5 years ago
- TCP/IP controlled VPI JTAG Interface.☆70Jan 16, 2025Updated last year
- verification of simple axi-based cache☆19May 14, 2019Updated 6 years ago
- 1-Click AI Models by DigitalOcean Gradient • AdDeploy popular AI models on DigitalOcean Gradient GPU virtual machines with just a single click. Zero configuration with optimized deployments.
- ☆43Apr 17, 2026Updated 2 weeks ago
- Verilog implementation of 1024 bit Hybrid Montgomery Multiplication/Exponentiation☆14Nov 28, 2019Updated 6 years ago
- My RV64 CPU (Work in progress)☆19Dec 22, 2022Updated 3 years ago
- Examples of unions, interfaces, and assertions in SystemVerilog☆13Aug 31, 2013Updated 12 years ago
- amba3 apb/axi vip☆52Feb 24, 2015Updated 11 years ago
- Project aimed at implementing floating point operators using the DSP48E1 slice.☆29Mar 29, 2013Updated 13 years ago
- Tcore是我在暑假参与清华陈渝教授带领的summer school时和同来参与研修的东南大学李可然同学决定一起做的在一个基于Rcore衍生项目，终极目标是一起做出一个基于Riscv的Cpu并且开发一个可以移植到该Cpu上完整的操作系统，将操作系统继续钻研下去☆14Oct 23, 2019Updated 6 years ago
- Wrappers for open source FPU hardware implementations.☆37Nov 27, 2025Updated 5 months ago
- [UNRELEASED] FP div/sqrt unit for transprecision☆27Sep 9, 2025Updated 7 months ago
- Proton VPN Special Offer - Get 70% off • AdSpecial partner offer. Trusted by over 100 million users worldwide. Tested, Approved and Recommended by Experts.
- Cluster-level matrix unit integration into GPUs, implemented in Chipyard SoC☆54Jan 20, 2026Updated 3 months ago
- Github repository of the AIStats 2024 paper: DE-HNN: An effective neural model for Circuit Netlist representation☆16Sep 3, 2025Updated 8 months ago
- ☆10Oct 15, 2021Updated 4 years ago
- ☆63Feb 18, 2019Updated 7 years ago
- RISC-V Configuration Validator☆82Apr 16, 2026Updated 2 weeks ago
- ☆89Apr 10, 2026Updated 3 weeks ago
- This repository contains a SDSoC Project which includes an implementation of a 3-layered artificial neural network (testphase only). It c…☆12Oct 7, 2016Updated 9 years ago