Build mini linux for your own RISC-V emulator!
☆25Sep 11, 2024Updated 2 years ago
Alternatives and similar repositories for rvcore-mini-linux
Users that are interested in rvcore-mini-linux are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- 给NEMU移植Linux Kernel!☆23Jun 1, 2025Updated last year
- Embedded Development Framework for ECOS SoC Chip.☆18Updated this week
- nscscc2024，HPU河南理工大学参赛作品，两仪处理器☆13Aug 24, 2024Updated 2 years ago
- ☆15Jul 28, 2026Updated 3 months ago
- Vivado in GitLab-Runner for GitLab CI/CD☆10Oct 27, 2022Updated 4 years ago
- 1-Click AI Models by DigitalOcean Gradient • AdDeploy popular AI models on DigitalOcean Gradient GPU virtual machines with just a single click. Zero configuration with optimized deployments.
- ☆21May 26, 2025Updated last year
- 本项目已被合并至官方Chiplab中☆14Jan 13, 2025Updated last year
- ☆40Jul 22, 2025Updated last year
- ☆25Aug 11, 2024Updated 2 years ago
- A tool to decode RISC-V and LoongArch and MIPS instructions in gtkwave☆35Apr 13, 2025Updated last year
- Second Prize in NSCSCC 2024. An out-of-order CPU designed by NoAXI team from HDU. 2024年全国大学生计算机系统能力大赛CPU设计赛（龙芯杯）团队赛二等奖作品☆26Sep 14, 2024Updated 2 years ago
- GPGPU-Sim 中文注释版代码，包含 GPGPU-Sim 模 拟器的最新版代码，经过中文注释，以帮助中文用户更好地理解和使用该模拟器。☆30Dec 18, 2024Updated last year
- 体系结构研讨 + ysyx高阶大纲 (WIP☆219Sep 24, 2026Updated last month
- ☆68Aug 5, 2024Updated 2 years ago
- Deploy open-source AI quickly and easily - Special Bonus Offer • AdRunpod Hub is built for open source. One-click deployment and autoscaling endpoints without provisioning your own infrastructure.
- Basic chisel difftest environment for RTL design (WIP☆21Mar 8, 2025Updated last year
- An RTL-to-Chip Silicon Design Solution.☆79Updated this week
- MCP server to read waveform files☆48Updated this week
- QuardStar Tutorial is all you need !☆20Sep 11, 2024Updated 2 years ago
- VSH（SHell for Visualizing vcd file）项目为数字波形文件命令行查看器。☆25Dec 8, 2025Updated 10 months ago
- Lower chisel memories to SRAM macros☆13Mar 25, 2024Updated 2 years ago
- Nix template for the chisel-based industrial designing flows.☆58Jul 21, 2026Updated 3 months ago
- ☆12Sep 18, 2024Updated 2 years ago
- High performance LA32R out-of-order processor core. (NSCSCC 2023 Special Prize)☆101Aug 29, 2023Updated 3 years ago
- Deploy on Railway without the complexity - Free Credits Offer • AdConnect your repo and Railway handles the rest with instant previews. Quickly provision container image services, databases, and storage volumes.
- How to make undergraduates or new graduates ready for advanced computer architecture research or modern CPU design☆681Aug 13, 2024Updated 2 years ago
- 适用于龙芯杯团队赛入门选手的应急cache模块☆38Mar 13, 2024Updated 2 years ago
- ☆30Jun 19, 2025Updated last year
- ☆19Jun 24, 2024Updated 2 years ago
- An implementation of the GDB Remote Serial Protocol to help you adding debug mode on emulator☆95Mar 18, 2026Updated 7 months ago
- The Scala parser to parse riscv/riscv-opcodes generate☆26Jan 21, 2026Updated 9 months ago
- A fork of Xiangshan for AI☆64Updated this week
- ☆35Aug 22, 2023Updated 3 years ago
- Mirror of https://gitee.com/loongson-edu/open-la500.git☆30Jan 2, 2025Updated last year
- Deploy to Railway using AI coding agents - Free Credits Offer • AdUse Claude Code, Codex, OpenCode, and more. Autonomous software development now has the infrastructure to match with Railway.
- ☆98Nov 12, 2025Updated 11 months ago
- A simple OoO processor developed by njuallen and wierton, it won 2nd prize in LoongsonCup18.☆31Feb 10, 2020Updated 6 years ago
- ☆13Oct 18, 2026Updated last week
- Linux on RISC-V on FPGA (LOROF): RV64GC Sv39 Quad-Core Superscalar Out-of-Order Virtual Memory CPU☆19Oct 24, 2026Updated last week
- gem5 FS模式实验手册☆49Mar 8, 2023Updated 3 years ago
- A Customized ASIC framework for Retro Stuff☆37Updated this week
- Xiangshan deterministic workloads generator☆29Oct 14, 2026Updated 2 weeks ago