pku-liang / Cement
The Next-gen Language & Compiler Powering Efficient Hardware Design
☆25Updated last month
Alternatives and similar repositories for Cement:
Users that are interested in Cement are comparing it to the libraries listed below
- ☆12Updated last month
- ☆39Updated last month
- Domain-Specific Architecture Generator 2☆21Updated 2 years ago
- HeteroHalide: From Image Processing DSL to Efficient FPGA Acceleration☆15Updated 4 years ago
- A collection of tests and benchmarks for the Arc simulation backend of CIRCT☆27Updated last week
- An LLVM pass to prove that an II works for the given loop for Vitis HLS☆11Updated 3 years ago
- A hardware synthesis framework with multi-level paradigm☆36Updated last month
- ☆23Updated 4 years ago
- ☆17Updated 7 months ago
- Parendi: Thousand-way Parallel RTL Simulation on the Graphcore IPU☆19Updated 10 months ago
- Papers, Posters, Presentations, Documentation...☆18Updated last year
- NPUsim: Full-Model, Cycle-Level, and Value-Aware Simulator for DNN Accelerators☆26Updated last month
- ☆32Updated this week
- CIRCT-based HLS compilation flows, debugging, and cosimulation tools.☆48Updated last year
- A Hardware Pipeline Description Language☆44Updated last year
- Polyhedral High-Level Synthesis in MLIR☆30Updated last year
- Meta-Repository for Bespoke Silicon Group's Manycore Architecture (A.K.A HammerBlade)☆38Updated 2 months ago
- ☆16Updated 3 years ago
- An Open-Source SCAlable Interface for ISA Extensionsfor RISC-V Processors. New Version:☆14Updated 11 months ago
- Dynamically Reconfigurable Architecture Template and Cycle-level Microarchitecture Simulator for Dataflow AcCelerators☆28Updated last year
- A Rocket-based RISC-V superscalar in-order core☆29Updated 2 weeks ago
- A synthesis flow for hybrid processing-in-RRAM modes☆12Updated 3 years ago
- Implementation of Pythia: A Customizable Hardware Prefetching Framework Using Online Reinforcement Learning in Chisel HDL. To know more, …☆13Updated 3 years ago
- ☆11Updated 3 years ago
- 📥 🎯 (1,4/4) an MLIR-based toolchain with Vitis HLS LLVM input/output targeting FPGAs.☆13Updated 2 years ago
- ☆15Updated 2 years ago
- ETHZ Heterogeneous Accelerated Compute Cluster.☆31Updated this week
- PAAS: A System Level Simulator for Heterogeneous (CPU-FPGA) Computing Systems☆43Updated 3 years ago
- The RTL source for AnyCore RISC-V☆31Updated 2 years ago