Alternatives and similar repositories for Utility

Users that are interested in Utility are comparing it to the libraries listed below

• OpenXiangShan / CoupledL2
  Open-source non-blocking L2 cache
  ☆52Updated this week
• OpenXiangShan / YunSuan
  This repo includes XiangShan's function units
  ☆29Updated last week
• ucb-bar / shuttle
  A Rocket-based RISC-V superscalar in-order core
  ☆38Updated 4 months ago
• circt / arc-tests
  A collection of tests and benchmarks for the Arc simulation backend of CIRCT
  ☆35Updated last week
• jiegec / fpu-wrappers
  Wrappers for open source FPU hardware implementations.
  ☆37Updated 2 months ago
• jiegec / rocket-chip-vcu128
  Run Rocket Chip on VCU128
  ☆30Updated 3 months ago
• ucb-bar / radiance
  A Heterogeneous GPU Platform for Chipyard SoC
  ☆42Updated this week
• chipsalliance / playground
  chipyard in mill :P
  ☆77Updated 2 years ago
• chipsalliance / rocket-chip-inclusive-cache
  An RTL generator for a last-level shared inclusive TileLink cache controller
  ☆24Updated last year
• ucb-bar / chisel-gui
  A prototype GUI for chisel-development
  ☆51Updated 5 years ago
• chipsalliance / espresso
  ☆41Updated 2 months ago
• chipsalliance / diplomacy
  ☆23Updated 2 months ago
• freechipsproject / chisel-cheatsheet
  Chisel Cheatsheet
  ☆34Updated 2 years ago
• pku-liang / Cement
  The Next-gen Language & Compiler Powering Efficient Hardware Design
  ☆36Updated last year
• ucb-bar / cva6-wrapper
  Wrapper for ETH Ariane Core
  ☆22Updated 5 months ago
• RISMicroDevices / CHIron
  Open-source AMBA CHI infrastructures (supporting Issue B, E.b)
  ☆33Updated this week
• OpenXiangShan / fudian
  Open source high performance IEEE-754 floating unit
  ☆89Updated last year
• IBM / chiffre
  A fault-injection framework using Chisel and FIRRTL
  ☆36Updated 4 months ago
• arch-simulator-sig / chisel-env
  Basic chisel difftest environment for RTL design (WIP
  ☆20Updated 11 months ago
• sequencer / arithmetic
  ☆33Updated 10 months ago
• CMU-SAFARI / Pythia-HDL
  Implementation of Pythia: A Customizable Hardware Prefetching Framework Using Online Reinforcement Learning in Chisel HDL. To know more, …
  ☆17Updated 4 years ago
• pulp-platform / culsans
  Tightly-coupled cache coherence unit for CVA6 using the ACE protocol
  ☆37Updated last year
• freechipsproject / ip-contributions
  For contributions of Chisel IP to the chisel community.
  ☆70Updated last year
• jiegec / chisel-memory-lower
  Lower chisel memories to SRAM macros
  ☆13Updated last year
• sequencer / zaozi
  A eDSL framework based on Scala and MLIR, focusing on the Hardware design.
  ☆65Updated this week
• ljwljwljwljw / DiplomaticBackend
  ☆17Updated 3 years ago
• OpenXiangShan / HuanCun
  Open-source high-performance non-blocking cache
  ☆92Updated 2 months ago
• pulp-platform / redmule
  ☆90Updated last month
• meow-chip / MeowV64
  A superscalar RISC-V CPU with out-of-order execution and multi-core support
  ☆61Updated 3 years ago
• CTSRD-CHERI / SIMTight
  Synthesisable SIMT-style RISC-V GPGPU
  ☆48Updated 7 months ago