OSCPU / ysyxSoC
☆79Updated last month
Alternatives and similar repositories for ysyxSoC:
Users that are interested in ysyxSoC are comparing it to the libraries listed below
- ☆58Updated 2 months ago
- ☆61Updated 7 months ago
- ☆63Updated 2 years ago
- 一生一芯 , ysyx , npc . the repo of the YSYX project . a riscv-64 CPU . writing .☆26Updated 2 years ago
- ☆63Updated last month
- "aura" my super-scalar O3 cpu core☆24Updated 9 months ago
- Open Source Chip Project by University (OSCPU) - Zhoushan Core☆49Updated 2 years ago
- ☆127Updated 3 weeks ago
- ☆20Updated last year
- ☆60Updated last year
- AXI协议规范中文翻译版☆141Updated 2 years ago
- 体系结构研讨 + ysyx高阶大纲 (WIP☆143Updated 5 months ago
- CPU Design Based on RISCV ISA☆95Updated 9 months ago
- ☆41Updated 2 years ago
- A tool to decode RISC-V and LoongArch and MIPS instructions in gtkwave☆30Updated 11 months ago
- A RISC-V RV32I ISA Single Cycle CPU☆22Updated last year
- a training-target implementation of rv32im, designed to be simple and easy to understand☆55Updated 3 years ago
- ☆74Updated this week
- ☆17Updated last year
- A 16-bit by 16-bit signed binary multiplier based on the Radix-4 Booth algorithm and Wallace Tree reduction☆39Updated 7 months ago
- Pick your favorite language to verify your chip.☆40Updated last week
- verilog module add prefix script 可用于ysyx项目添加学号☆13Updated last year
- upgrade to e203 (a risc-v core)☆40Updated 4 years ago
- An AXI4 crossbar implementation in SystemVerilog☆137Updated last month
- Lab exercises for Chisel in the digital electronics 2 course at DTU☆190Updated last week
- ☆62Updated 4 years ago
- Collect some IC textbooks for learning.☆126Updated 2 years ago
- Open IP in Hardware Description Language.☆19Updated last year
- A Verilator based SoC simulator that allows you to define AXI Slave interface in software.☆47Updated 4 months ago
- ☆36Updated 6 years ago