OSCPU / ysyxSoCLinks
☆89Updated last month
Alternatives and similar repositories for ysyxSoC
Users that are interested in ysyxSoC are comparing it to the libraries listed below
Sorting:
- ☆86Updated this week
- ☆67Updated last year
- Open Source Chip Project by University (OSCPU) - Zhoushan Core☆53Updated 3 years ago
- 体系结构研讨 + ysyx高阶大纲 (WIP☆186Updated last year
- "aura" my super-scalar O3 cpu core☆24Updated last year
- ☆68Updated 9 months ago
- ☆64Updated 3 years ago
- ☆70Updated 2 years ago
- Lab exercises for Chisel in the digital electronics 2 course at DTU☆214Updated 5 months ago
- ☆204Updated 4 months ago
- Pick your favorite language to verify your chip.☆72Updated this week
- ☆45Updated 3 years ago
- Collect some IC textbooks for learning.☆169Updated 3 years ago
- A RISC-V RV32I ISA Single Cycle CPU☆25Updated 5 months ago
- ☆111Updated this week
- a training-target implementation of rv32im, designed to be simple and easy to understand☆61Updated 3 years ago
- A tool to decode RISC-V and LoongArch and MIPS instructions in gtkwave☆31Updated 7 months ago
- ☆31Updated 3 months ago
- AXI协议规范中文翻译版☆165Updated 3 years ago
- Modern co-simulation framework for RISC-V CPUs☆159Updated this week
- GPGPU supporting RISCV-V, developed with verilog HDL☆122Updated 8 months ago
- Documentation for XiangShan Design☆35Updated 3 weeks ago
- 关于移植模型至gemmini的文档☆30Updated 3 years ago
- ☆18Updated 2 years ago
- CPU Design Based on RISCV ISA☆122Updated last year
- An AXI4 crossbar implementation in SystemVerilog☆178Updated 2 months ago
- XiangShan Frontend Develop Environment☆68Updated last week
- 一生一芯 , ysyx , npc . the repo of the YSYX project . a riscv-64 CPU . writing .☆32Updated 3 years ago
- A Chisel RTL generator for network-on-chip interconnects☆218Updated this week
- ☆22Updated 2 years ago