Alternatives and similar repositories for ysyxSoC

Users that are interested in ysyxSoC are comparing it to the libraries listed below

• OSCPU / yosys-sta
  ☆74Updated 3 months ago
• ysyx-ta / ysyx-summer-readings
  ☆66Updated 11 months ago
• OSCPU-Zhoushan / Zhoushan
  Open Source Chip Project by University (OSCPU) - Zhoushan Core
  ☆51Updated 3 years ago
• Yawei-Ding / ysyx_riscv64_cpu
  ☆68Updated 2 years ago
• tastynoob / aura-core
  "aura" my super-scalar O3 cpu core
  ☆24Updated last year
• arch-simulator-sig / advanced-computer-architecture
  体系结构研讨 + ysyx高阶大纲 (WIP
  ☆176Updated 9 months ago
• lizhirui / DreamCore
  ☆64Updated 2 years ago
• OSCPU / chisel-playground
  ☆67Updated 5 months ago
• lizhirui / AXI_spec_chinese
  AXI协议规范中文翻译版
  ☆159Updated 3 years ago
• RV-BOSC / OpenNoC
  ☆176Updated last month
• shawn110285 / Cookabarra
  a training-target implementation of rv32im, designed to be simple and easy to understand
  ☆60Updated 3 years ago
• OpenXiangShan / difftest
  Modern co-simulation framework for RISC-V CPUs
  ☆147Updated this week
• schoeberl / chisel-lab
  Lab exercises for Chisel in the digital electronics 2 course at DTU
  ☆205Updated last month
• kaitoukito / Integrated-Circuit-Textbooks
  Collect some IC textbooks for learning.
  ☆150Updated 2 years ago
• OpenXiangShan / XS-Verilog-Library
  ☆43Updated 3 years ago
• wataru030-XIAOHEI / My-RISCV64-CORE-writing
  一生一芯 ， ysyx ， npc . the repo of the YSYX project . a riscv-64 CPU . writing .
  ☆29Updated 3 years ago
• xiaoerlang0359 / E203plus
  upgrade to e203 (a risc-v core)
  ☆44Updated 4 years ago
• peilin-chen / Zhulong-RISCV-CPU
  CPU Design Based on RISCV ISA
  ☆118Updated last year
• CherrySprings / CherrySprings
  ☆18Updated 2 years ago
• FurryAcetylCoA / gtkwave-filter-process-RISC
  A tool to decode RISC-V and LoongArch and MIPS instructions in gtkwave
  ☆31Updated 3 months ago
• XS-MLVP / picker
  Pick your favorite language to verify your chip.
  ☆60Updated this week
• OpenXiangShan / XiangShan-Design-Doc
  Documentation for XiangShan Design
  ☆29Updated 2 weeks ago
• OpenXiangShan / GEM5
  ☆93Updated this week
• dpretet / axi-crossbar
  An AXI4 crossbar implementation in SystemVerilog
  ☆164Updated last month
• github-3rr0r / RV32ISC
  A RISC-V RV32I ISA Single Cycle CPU
  ☆24Updated 2 months ago
• Heresyrac / Gemmini_doc
  关于移植模型至gemmini的文档
  ☆28Updated 3 years ago
• THU-DSP-LAB / ventus-gpgpu-verilog
  GPGPU supporting RISCV-V, developed with verilog HDL
  ☆104Updated 5 months ago
• wuzeyou / Multiplier16X16
  Classic Booth Code, Wallace Tree, and SquareRoot Carry Select Adder
  ☆117Updated 12 years ago
• Jpz-sdju / trinity
  ☆24Updated last week
• OSCPU / ysyx
  一生一芯的信息发布和内容网站
  ☆132Updated last year