OSCPU / ysyxSoCLinks
☆87Updated 2 weeks ago
Alternatives and similar repositories for ysyxSoC
Users that are interested in ysyxSoC are comparing it to the libraries listed below
Sorting:
- ☆83Updated 5 months ago
- ☆67Updated last year
- Open Source Chip Project by University (OSCPU) - Zhoushan Core☆52Updated 3 years ago
- "aura" my super-scalar O3 cpu core☆24Updated last year
- 体系结构研讨 + ysyx高阶大纲 (WIP☆180Updated 11 months ago
- ☆70Updated 2 years ago
- ☆67Updated 7 months ago
- ☆64Updated 3 years ago
- ☆44Updated 3 years ago
- A tool to decode RISC-V and LoongArch and MIPS instructions in gtkwave☆31Updated 5 months ago
- ☆195Updated 3 months ago
- Collect some IC textbooks for learning.☆165Updated 3 years ago
- a training-target implementation of rv32im, designed to be simple and easy to understand☆61Updated 3 years ago
- ☆18Updated 2 years ago
- AXI协议规范中文翻译版☆163Updated 3 years ago
- ☆28Updated 2 months ago
- CPU Design Based on RISCV ISA☆122Updated last year
- Modern co-simulation framework for RISC-V CPUs☆157Updated this week
- GPGPU supporting RISCV-V, developed with verilog HDL☆113Updated 7 months ago
- Lab exercises for Chisel in the digital electronics 2 course at DTU☆210Updated 3 months ago
- An AXI4 crossbar implementation in SystemVerilog☆175Updated last month
- ☆103Updated last week
- Verilog Implementation of TAGE based predictor by Andre Seznec and Pierre Michaud☆21Updated 7 years ago
- Pick your favorite language to verify your chip.☆70Updated last week
- upgrade to e203 (a risc-v core)☆44Updated 5 years ago
- ☆156Updated this week
- 关于移植模型至gemmini的文档☆30Updated 3 years ago
- Vector processor for RISC-V vector ISA☆128Updated 4 years ago
- Documentation for XiangShan Design☆32Updated this week
- A Chisel RTL generator for network-on-chip interconnects☆211Updated last month