Alternatives and similar repositories for nontrivial-mips

Users that are interested in nontrivial-mips are comparing it to the libraries listed below

• cnrv / riscv-soc-book
  关于RISC-V你所需要知道的一切
  ☆561Updated 2 years ago
• trivialmips / TrivialMIPS
  MIPS32 CPU implemented in SystemVerilog, with superscalar and FPU support
  ☆106Updated 6 years ago
• z4yx / NaiveMIPS-HDL
  Naïve MIPS32 SoC implementation
  ☆115Updated 5 years ago
• Trinkle23897 / mips32-cpu
  奋战一学期，造台计算机（编译出的bit文件在release中，可以直接食用）
  ☆128Updated 5 years ago
• Silverster98 / bit_nscscc_suggestion
  为了更好地帮助后来的同学参加龙芯杯，草拟了这份建议，望对后来人有所帮助
  ☆127Updated 4 years ago
• loongson-education / nscscc-wiki
  NSCSCC 信息整合
  ☆244Updated 4 years ago
• xyongcn / LoongsonCsprj2017
  Computer System Project for Loongson FPGA Board in 2017
  ☆52Updated 7 years ago
• OSCPU / NutShell-doc
  ☆122Updated 2 years ago
• zach0zhang / Single_instruction_cycle_OpenMIPS
  通过学习《自己动手写CPU》，将书中实现的兼容MIPS32指令集架构的处理器——OpenMIPS（五级流水线结构），简化成单指令周期实现的处理器
  ☆205Updated 3 years ago
• OSCPU / NutShell
  RISC-V SoC designed by students in UCAS
  ☆1,465Updated 5 months ago
• MaxXSoft / Fuxi
  Fuxi (伏羲) is a 32-bit pipelined RISC-V processor written in Chisel3.
  ☆172Updated 3 years ago
• hehao98 / RISCV-Simulator
  A Simple RISC-V CPU Simulator with 5 Stage Pipeline, Branch Prediction and Cache Simulation
  ☆184Updated last year
• shinezyy / micro-arch-training
  How to make undergraduates or new graduates ready for advanced computer architecture research or modern CPU design
  ☆578Updated 10 months ago
• NJU-ProjectN / nvboard
  NJU Virtual Board
  ☆281Updated last week
• LvNA-system / labeled-RISC-V
  ☆169Updated 3 years ago
• cnrv / home
  为推广RISC-V尽些薄力
  ☆311Updated 2 years ago
• whik / e200_opensource
  The Ultra-Low Power RISC Core
  ☆48Updated 5 years ago
• OpenXiangShan / NEMU
  ☆280Updated last week
• skyzh / RISCV-Simulator
  💻 RISC-V Simulator of RV32I ISA. 5-stage pipeline / out-of-order execution with Tomasulo algorithm and Speculation. Support runtime visu…
  ☆201Updated 4 years ago
• thu-cs-lab / supervisor-rv
  计算机组成原理课程 RISC-V 监控程序，支持 32 位和 64 位
  ☆117Updated 9 months ago
• OSCPU / ysyx
  一生一芯的信息发布和内容网站
  ☆131Updated last year
• lmxyy / Computer-Architecture-Task-2
  Riscv32 CPU Project
  ☆93Updated 7 years ago
• z4yx / supervisor-mips32
  计算机组成原理课程32位监控程序
  ☆47Updated 5 years ago
• RickyTino / MangoMIPS32
  A softcore microprocessor of MIPS32 architecture.
  ☆40Updated 11 months ago
• chyyuu / compiler_course_info
  compiler course info
  ☆248Updated last year
• mlzeng / CSC2020-USTC-FlammingMyCompiler
  全国大学生计算机系统能力大赛编译系统设计赛项目
  ☆245Updated 4 years ago
• plctlab / PLCT-Weekly
  软件所PLCT实验室在开源领域的不定期简报
  ☆631Updated 2 weeks ago
• arch-simulator-sig / advanced-computer-architecture
  体系结构研讨 + ysyx高阶大纲 (WIP
  ☆171Updated 8 months ago
• Summer-Summer / ComputerArchitectureLab
  This repository is used to release the experimental assignments of Computer Architecture Course from USTC
  ☆39Updated 5 years ago
• THU-DSP-LAB / ventus-gpgpu
  GPGPU processor supporting RISCV-V extension, developed with Chisel HDL
  ☆754Updated this week