trivialmips / nontrivial-mips
NonTrivial-MIPS is a synthesizable superscalar MIPS processor with branch prediction and FPU support, and it is capable of booting linux.
☆574Updated 4 years ago
Related projects ⓘ
Alternatives and complementary repositories for nontrivial-mips
- Naïve MIPS32 SoC implementation☆113Updated 4 years ago
- NSCSCC 信息整合☆220Updated 3 years ago
- MIPS32 CPU implemented in SystemVerilog, with superscalar and FPU support☆104Updated 5 years ago
- 关于RISC-V你所需要知道的一切☆542Updated last year
- ☆116Updated 2 years ago
- 为了更好地帮助后来的同学参加龙芯杯，草拟了这份建议，望对后来人有所帮助☆114Updated 4 years ago
- How to make undergraduates or new graduates ready for advanced computer architecture research or modern CPU design☆476Updated 3 months ago
- 通过学习《自己动手写CPU》，将书中实现的兼容MIPS32指令集架构的处理器——OpenMIPS（五级流水线结构），简化成单指令周期实现的处理器☆192Updated 2 years ago
- 奋战一学期，造台计算机（编译出的bit文件在release中，可以直接食用）☆126Updated 5 years ago
- ☆236Updated this week
- 《从零开始的RISC-V模拟器开发》配套的PPT和教学资料☆194Updated 3 years ago
- Computer System Project for Loongson FPGA Board in 2017☆50Updated 6 years ago
- NJU Virtual Board☆235Updated 3 months ago
- 为推广RISC-V尽些薄力☆306Updated last year
- A minimal, modularized, and machine-independent hardware abstraction layer☆451Updated 2 months ago
- Documentation for XiangShan☆350Updated last week
- NJU EMUlator, a full system x86/mips32/riscv32/riscv64 emulator for teaching☆897Updated last month
- RISC-V SoC designed by students in UCAS☆1,397Updated 2 weeks ago
- Fuxi (伏羲) is a 32-bit pipelined RISC-V processor written in Chisel3.☆162Updated 3 years ago
- 软件所PLCT实验室在开源领域的不定期简报☆585Updated last week
- 一生一芯的信息发布和内容网站☆123Updated last year
- A translation project of the RISC-V reader☆175Updated 10 months ago
- 5 stage pipelined MIPS-32 processor☆57Updated 4 years ago
- A Simple RISC-V CPU Simulator with 5 Stage Pipeline, Branch Prediction and Cache Simulation☆162Updated 7 months ago
- ☆165Updated 3 years ago
- 全国大学生计算机系统能力大赛编译系统设计赛项目☆242Updated 3 years ago
- Riscv32 CPU Project☆82Updated 6 years ago
- riscv资料、论文等☆140Updated 6 years ago
- 计算机组成原理课程 RISC-V 监控程序，支持 32 位和 64 位☆114Updated 2 months ago
- GPGPU processor supporting RISCV-V extension, developed with Chisel HDL☆634Updated this week