trivialmips / nontrivial-mips
NonTrivial-MIPS is a synthesizable superscalar MIPS processor with branch prediction and FPU support, and it is capable of booting linux.
☆592Updated 4 years ago
Alternatives and similar repositories for nontrivial-mips:
Users that are interested in nontrivial-mips are comparing it to the libraries listed below
- Naïve MIPS32 SoC implementation☆113Updated 4 years ago
- MIPS32 CPU implemented in SystemVerilog, with superscalar and FPU support☆106Updated 5 years ago
- 为了更好地帮助后来的同学参加龙芯杯,草拟了这份建议,望对后来人有所帮助☆122Updated 4 years ago
- 关于RISC-V你所需要知道的一切☆552Updated last year
- ☆122Updated 2 years ago
- A Simple RISC-V CPU Simulator with 5 Stage Pipeline, Branch Prediction and Cache Simulation☆180Updated 11 months ago
- NSCSCC 信息整合☆234Updated 4 years ago
- NJU Virtual Board☆265Updated 3 months ago
- Computer System Project for Loongson FPGA Board in 2017☆52Updated 6 years ago
- ☆268Updated last week
- 💻 RISC-V Simulator of RV32I ISA. 5-stage pipeline / out-of-order execution with Tomasulo algorithm and Speculation. Support runtime visu…☆201Updated 4 years ago
- How to make undergraduates or new graduates ready for advanced computer architecture research or modern CPU design☆533Updated 7 months ago
- 奋战一学期,造台计算机(编译出的bit文件在release中,可以直接食用)☆126Updated 5 years ago
- Documentation for XiangShan☆409Updated last week
- RISC-V SoC designed by students in UCAS☆1,443Updated 2 months ago
- Riscv32 CPU Project☆86Updated 7 years ago
- 通过学习《自己动手写CPU》,将书中实现的兼容MIPS32指令集架构的处理器——OpenMIPS(五级流水线结构),简化成单指令周期实现的处理器☆195Updated 3 years ago
- Fuxi (伏羲) is a 32-bit pipelined RISC-V processor written in Chisel3.☆170Updated 3 years ago
- 为推广RISC-V尽些薄力☆311Updated last year
- A minimal, modularized, and machine-independent hardware abstraction layer☆482Updated 2 months ago
- ☆169Updated 3 years ago
- The wrapper repo for NJU ICS PA.☆446Updated 6 months ago
- A translation project of the RISC-V reader☆174Updated last year
- This repository is used to release the experimental assignments of Computer Architecture Course from USTC☆37Updated 5 years ago
- NJU EMUlator, a full system x86/mips32/riscv32/riscv64 emulator for teaching☆973Updated last month
- 体系结构研讨 + ysyx高阶大纲 (WIP☆146Updated 5 months ago
- 一步一步写MIPS CPU☆785Updated 3 years ago
- 《从零开始的RISC-V模拟器开发》配套的PPT和教学资料☆215Updated 3 years ago
- Simple RISC-V 3-stage Pipeline in Chisel☆563Updated 7 months ago
- 一生一芯的信息发布和内容网站☆128Updated last year