Fuxi (伏羲) is a 32-bit pipelined RISC-V processor written in Chisel3.
☆186Oct 26, 2026Updated this week
Alternatives and similar repositories for Fuxi
Users that are interested in Fuxi are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- The Gee (寂) Operating System, written in YuLang.☆34Oct 5, 2026Updated 3 weeks ago
- The Yu (羽) programming language.☆81Oct 5, 2026Updated 3 weeks ago
- Uranus MIPS processor by MaxXing & USTB NSCSCC team☆38Dec 14, 2019Updated 6 years ago
- riscv32i-cpu☆18Nov 20, 2020Updated 5 years ago
- The Project TinyMIPS is dedicated to enabling undergraduates to build a complete computer system from scratch.☆36Feb 28, 2020Updated 6 years ago
- Managed Kubernetes at scale on DigitalOcean • AdDigitalOcean Kubernetes includes the control plane, bandwidth allowance, container registry, automatic updates, and more for free.
- RISC-V SoC designed by students in UCAS☆1,561Updated this week
- A simple OoO processor developed by njuallen and wierton, it won 2nd prize in LoongsonCup18.☆31Feb 10, 2020Updated 6 years ago
- Simple RISC-V 3-stage Pipeline in Chisel☆620Aug 9, 2024Updated 2 years ago
- A RISC-V Core (RV32I) written in Chisel HDL☆110Oct 19, 2026Updated last week
- Learning how to make RISC-V 32bit CPU with Chisel☆71Sep 17, 2021Updated 5 years ago
- Build lexers and parsers by deriving traits.☆25Aug 3, 2026Updated 2 months ago
- HITSZ 404 NOT FOUND NSCSCC22 project☆16Sep 8, 2022Updated 4 years ago
- Linux-capable superscalar out-of-order RISC core (with Cache& MMU) and SoC, having been verified on Xilinx Kintex-7 FPGA.☆56Aug 14, 2024Updated 2 years ago
- 5-stage RISC-V core (RV32IM) with pipelining designed for educational purposes by RPTU Kaiserslautern, Germany☆16Dec 4, 2025Updated 10 months ago
- Managed hosting for WordPress and PHP on Cloudways • AdManaged hosting for WordPress, Magento, Laravel, or PHP apps, on multiple cloud providers. Deploy in minutes on Cloudways by DigitalOcean.
- Take your first step in writing a compiler. Implemented in Rust.☆16Apr 17, 2023Updated 3 years ago
- Super fast RISC-V ISA emulator for XiangShan processor☆352Updated this week
- LoveLonelyTime's RISC-V core basic version, RV32I, five pipeline stages.☆17Apr 2, 2024Updated 2 years ago
- A riscv emulator.☆19Feb 5, 2024Updated 2 years ago
- 北京地铁费用系统网页版:GUI可视化界面(Beijing Metro Expense System Web Edition: GUI Visualization Interface)☆11Dec 5, 2021Updated 4 years ago
- ☆68Aug 5, 2024Updated 2 years ago
- Reasoning LLMs optimized for Chisel code generation☆26Jun 19, 2025Updated last year
- A series of RISC-V soft core processor written from scratch. Now, we're using all open-source toolchain (chisel, mill, verilator, NEMU, A…☆47Nov 8, 2023Updated 2 years ago
- CPU敏捷开发框架(龙芯杯2024)☆28Sep 6, 2024Updated 2 years ago
- Managed hosting for WordPress and PHP on Cloudways • AdManaged hosting for WordPress, Magento, Laravel, or PHP apps, on multiple cloud providers. Deploy in minutes on Cloudways by DigitalOcean.
- Superscalar dual-issue RISC-V processor☆20Aug 4, 2026Updated 2 months ago
- only display GPU☆10Mar 6, 2025Updated last year
- A template project for beginning new Chisel work☆710Feb 24, 2026Updated 8 months ago
- 通过输入关键词动态爬取图片保存于本地(Dynamically crawl images by entering keywords and save them locally)☆11Apr 22, 2019Updated 7 years ago
- 6-stage dual-issue in-order superscalar risc-v cpu☆15Sep 29, 2026Updated last month
- 北京科技大学芯炬社会实践团网页模型~(Beijing University of Science and Technology Core Torch Social Practice Group webpage model~)☆11Dec 15, 2021Updated 4 years ago
- 顺序单/双发射LA32R处理器 (龙芯杯2024) A LA32R CPU in chisel☆32Jan 25, 2026Updated 9 months ago
- 32-bit Superscalar RISC-V CPU☆1,324Sep 18, 2021Updated 5 years ago
- NSCSCC 信息整合☆254Feb 23, 2021Updated 5 years ago
- Deploy to Railway using AI coding agents - Free Credits Offer • AdUse Claude Code, Codex, OpenCode, and more. Autonomous software development now has the infrastructure to match with Railway.
- Basic chisel difftest environment for RTL design (WIP☆21Mar 8, 2025Updated last year
- 静态网页——贝壳航模(The first personal small project: static webpage - shell model)☆13Jun 29, 2021Updated 5 years ago
- BOOM's Simulation Accelerator.☆13Dec 16, 2021Updated 4 years ago
- ☆17Mar 26, 2025Updated last year
- An FPGA-based RISC-V CPU+SoC with a simple and extensible peripheral bus. 基于FPGA的RISC-V SoC,包含一个RV32I CPU、一个简单可扩展的总线、一些外设。☆442Sep 14, 2023Updated 3 years ago
- Superscalar RISC-V processor written in Clash.☆35Aug 23, 2022Updated 4 years ago
- Unofficial guide for ysyx students applying to ShanghaiTech University☆25Mar 31, 2026Updated 7 months ago