Alternatives and similar repositories for Fuxi:

Users that are interested in Fuxi are comparing it to the libraries listed below

• arch-simulator-sig / advanced-computer-architecture
  体系结构研讨 + ysyx高阶大纲 (WIP
  ☆137Updated 4 months ago
• OpenXiangShan / difftest
  Modern co-simulation framework for RISC-V CPUs
  ☆132Updated this week
• ysyx-ta / ysyx-summer-readings
  ☆61Updated 6 months ago
• NJU-ProjectN / nvboard
  NJU Virtual Board
  ☆251Updated last month
• OSCPU / NutShell-doc
  ☆120Updated 2 years ago
• OSCPU / yosys-sta
  ☆53Updated last month
• gzzyyxh / Quafu
  A small SoC with a pipeline 32-bit RISC-V CPU.
  ☆62Updated 2 years ago
• OSCPU / ysyx
  一生一芯的信息发布和内容网站
  ☆128Updated last year
• OSCPU / ysyxSoC
  ☆79Updated this week
• OSCPU-Zhoushan / Zhoushan
  Open Source Chip Project by University (OSCPU) - Zhoushan Core
  ☆47Updated 2 years ago
• OSCPU / ysyx-workbench
  ☆131Updated 5 months ago
• Silverster98 / bit_nscscc_suggestion
  为了更好地帮助后来的同学参加龙芯杯，草拟了这份建议，望对后来人有所帮助
  ☆118Updated 4 years ago
• LoveLonelyTime / Bergamot
  An exquisite superscalar RV32GC processor.
  ☆149Updated last month
• OSCPU / ysyx-exam
  ☆20Updated last year
• riscv-and-rust-and-decaf / riscv32i-cpu-chisel
  riscv32i-cpu
  ☆19Updated 4 years ago
• RickyTino / MangoMIPS32
  A softcore microprocessor of MIPS32 architecture.
  ☆39Updated 7 months ago
• OpenXiangShan / NEMU
  ☆257Updated this week
• SocialistDalao / UltraMIPS_NSCSCC
  UltraMIPS SoC composed of dual-issue cpu, pipeline Cache and systematic peripheral.
  ☆122Updated 7 months ago
• Groupsun / riscv-mini-five-stage
  This is my graduation project, a simple processor soft core, which implements RV32I ISA.
  ☆14Updated 5 years ago
• sycuricon / starship
  Run rocket-chip on FPGA
  ☆64Updated 3 months ago
• tastynoob / aura-core
  "aura" my super-scalar O3 cpu core
  ☆24Updated 8 months ago
• lizhirui / DreamCore
  ☆63Updated 2 years ago
• USTC-System-Courses / CECS-Lab
  ☆31Updated last year
• CherrySprings / CherrySprings
  ☆17Updated last year
• Yawei-Ding / ysyx_riscv64_cpu
  ☆57Updated last year
• shawn110285 / Cookabarra
  a training-target implementation of rv32im, designed to be simple and easy to understand
  ☆55Updated 3 years ago
• cyyself / soc-simulator
  A Verilator based SoC simulator that allows you to define AXI Slave interface in software.
  ☆46Updated 3 months ago
• OSCPU / chisel-playground
  ☆59Updated last week
• Superscalar-HIT-Core / Superscalar-HIT-Core-NSCSCC2020
  a Quad-issue, Out-of-order Superscalar MIPS Processor Implemented in SystemVerilog
  ☆46Updated last year
• Clo91eaf / PUA-MIPS
  NSCSCC 2023 The Second Prize. TEAM PUA FROM HDU.
  ☆10Updated 10 months ago