MaxXSoft / FuxiLinks
Fuxi (伏羲) is a 32-bit pipelined RISC-V processor written in Chisel3.
☆182Updated 4 years ago
Alternatives and similar repositories for Fuxi
Users that are interested in Fuxi are comparing it to the libraries listed below
Sorting:
- ☆125Updated 3 years ago
- 一生一芯的信息发布和内容网站☆136Updated 2 years ago
- Super fast RISC-V ISA emulator for XiangShan processor☆306Updated this week
- 体系结构研讨 + ysyx高阶大纲 (WIP☆193Updated last year
- Open Source Chip Project by University (OSCPU) - Zhoushan Core☆54Updated 3 years ago
- Modern co-simulation framework for RISC-V CPUs☆166Updated this week
- ☆160Updated 3 weeks ago
- An exquisite superscalar RV32GC processor.☆164Updated last year
- ☆67Updated last year
- ☆91Updated 3 months ago
- A small SoC with a pipeline 32-bit RISC-V CPU.☆66Updated 3 years ago
- ☆89Updated 2 months ago
- ☆19Updated 2 years ago
- Run rocket-chip on FPGA☆76Updated last month
- ☆70Updated 11 months ago
- XiangShan Frontend Develop Environment☆68Updated last week
- A Simple RISC-V CPU Simulator with 5 Stage Pipeline, Branch Prediction and Cache Simulation☆201Updated last year
- A Verilator based SoC simulator that allows you to define AXI Slave interface in software.☆51Updated 3 weeks ago
- NJU Virtual Board☆297Updated 4 months ago
- RISC-V模拟器,相关硬件实现`riscv-isa-sim`以及模拟器pk, bbl的指导手册☆53Updated 5 years ago
- ☆72Updated 2 years ago
- High performance LA32R out-of-order processor core. (NSCSCC 2023 Special Prize)☆82Updated 2 years ago
- Lab exercises for Chisel in the digital electronics 2 course at DTU☆218Updated last month
- UltraMIPS SoC composed of dual-issue cpu, pipeline Cache and systematic peripheral.☆146Updated last year
- ☆40Updated 2 years ago
- ☆64Updated 3 years ago
- Highly configurable out-of-order MIPS32 processor, capable of booting Linux.☆40Updated 2 years ago
- ☆214Updated last week
- A softcore microprocessor of MIPS32 architecture.☆40Updated last year
- a training-target implementation of rv32im, designed to be simple and easy to understand☆61Updated 4 years ago