ucb-bar / chiseltestView external linksLinks
The batteries-included testing and formal verification library for Chisel-based RTL designs.
☆233Aug 19, 2024Updated last year
Alternatives and similar repositories for chiseltest
Users that are interested in chiseltest are comparing it to the libraries listed below
Sorting:
- A dynamic verification library for Chisel.☆160Nov 9, 2024Updated last year
- A Library of Chisel3 Tools for Digital Signal Processing☆244Apr 29, 2024Updated last year
- Chisel/Firrtl execution engine☆155Aug 21, 2024Updated last year
- Provides various testers for chisel users☆100Jan 12, 2023Updated 3 years ago
- A template project for beginning new Chisel work☆690Jan 29, 2026Updated 2 weeks ago
- Simple RISC-V 3-stage Pipeline in Chisel☆603Aug 9, 2024Updated last year
- (System)Verilog to Chisel translator☆116May 20, 2022Updated 3 years ago
- chisel tutorial exercises and answers☆743Jan 6, 2022Updated 4 years ago
- For contributions of Chisel IP to the chisel community.☆70Nov 7, 2024Updated last year
- Flexible Intermediate Representation for RTL☆748Aug 20, 2024Updated last year
- Digital Design with Chisel☆895Updated this week
- ☆10Oct 15, 2021Updated 4 years ago
- Provides dot visualizations of chisel/firrtl circuits☆123Apr 14, 2023Updated 2 years ago
- Chisel examples and code snippets☆266Aug 1, 2022Updated 3 years ago
- A Scala library for Context-Dependent Environments☆50Apr 25, 2024Updated last year
- A coverage library for Chisel designs☆11Mar 12, 2020Updated 5 years ago
- Chisel: A Modern Hardware Design Language☆4,567Updated this week
- An Agile RISC-V SoC Design Framework with in-order cores, out-of-order cores, accelerators, and more☆2,138Updated this week
- Generator Bootcamp Material: Learn Chisel the Right Way☆1,109Sep 10, 2024Updated last year
- high-performance RTL simulator☆186Jun 19, 2024Updated last year
- BFM Tester for Chisel HDL☆14Nov 27, 2021Updated 4 years ago
- ☆33Mar 20, 2025Updated 10 months ago
- A Chisel RTL generator for network-on-chip interconnects☆226Nov 7, 2025Updated 3 months ago
- ☆19Jul 12, 2024Updated last year
- A Style Guide for the Chisel Hardware Construction Language☆109Jul 16, 2021Updated 4 years ago
- DFiant HDL (DFHDL): A Dataflow Hardware Descripition Language☆93Updated this week
- ☆87Jan 30, 2026Updated 2 weeks ago
- Chisel Cheatsheet☆35Apr 13, 2023Updated 2 years ago
- ☆367Sep 12, 2025Updated 5 months ago
- Rocket Chip Generator☆3,677Jan 9, 2026Updated last month
- Wrapper for ETH Ariane Core☆22Sep 2, 2025Updated 5 months ago
- educational microarchitectures for risc-v isa☆737Sep 1, 2025Updated 5 months ago
- Circuit IR Compilers and Tools☆2,031Updated this week
- ☆24Feb 11, 2021Updated 5 years ago
- chipyard in mill :P☆77Nov 20, 2023Updated 2 years ago
- A RISC-V Core (RV32I) written in Chisel HDL☆107Feb 3, 2026Updated last week
- SonicBOOM: The Berkeley Out-of-Order Machine☆2,072Feb 5, 2026Updated last week
- A Modular Open-Source Hardware Fuzzing Framework☆36Dec 14, 2021Updated 4 years ago
- A prototype GUI for chisel-development☆51Jun 9, 2020Updated 5 years ago