Alternatives and similar repositories for chiseltest:

Users that are interested in chiseltest are comparing it to the libraries listed below

• ucb-bar / dsptools
  A Library of Chisel3 Tools for Digital Signal Processing
  ☆237Updated last year
• schoeberl / chisel-examples
  Chisel examples and code snippets
  ☆250Updated 2 years ago
• ucb-bar / berkeley-hardfloat
  ☆322Updated 7 months ago
• ucb-bar / constellation
  A Chisel RTL generator for network-on-chip interconnects
  ☆196Updated this week
• chiselverify / chiselverify
  A dynamic verification library for Chisel.
  ☆148Updated 5 months ago
• schoeberl / chisel-lab
  Lab exercises for Chisel in the digital electronics 2 course at DTU
  ☆194Updated last month
• freechipsproject / chisel-testers
  Provides various testers for chisel users
  ☆100Updated 2 years ago
• IObundle / iob-cache
  Verilog Configurable Cache
  ☆178Updated 5 months ago
• chipsalliance / Cores-VeeR-EL2
  VeeR EL2 Core
  ☆274Updated last week
• ucb-bar / riscv-torture
  RISC-V Torture Test
  ☆193Updated 9 months ago
• cnrv / fpga-rocket-chip
  Wrapper for Rocket-Chip on FPGAs
  ☆132Updated 2 years ago
• openhwgroup / force-riscv
  Instruction Set Generator initially contributed by Futurewei
  ☆279Updated last year
• taichi-ishitani / tnoc
  Network on Chip Implementation written in SytemVerilog
  ☆174Updated 2 years ago
• pulp-platform / riscv-dbg
  RISC-V Debug Support for our PULP RISC-V Cores
  ☆250Updated 2 weeks ago
• chipsalliance / treadle
  Chisel/Firrtl execution engine
  ☆153Updated 8 months ago
• openhwgroup / cvfpu
  Parametric floating-point unit with support for standard RISC-V formats and operations as well as transprecision formats.
  ☆488Updated 2 months ago
• risclite / SuperScalar-RISCV-CPU
  SSRV(Super-Scalar RISC-V) --- Super-scalar out-of-order RV32IMC CPU core, 6.4 CoreMark/MHz.
  ☆212Updated 4 years ago
• ucb-bar / hwacha
  Microarchitecture implementation of the decoupled vector-fetch accelerator
  ☆153Updated last year
• bespoke-silicon-group / bsg_manycore
  Tile based architecture designed for computing efficiency, scalability and generality
  ☆252Updated this week
• freechipsproject / diagrammer
  Provides dot visualizations of chisel/firrtl circuits
  ☆119Updated 2 years ago
• pulp-platform / ara
  The PULP Ara is a 64-bit Vector Unit, compatible with the RISC-V Vector Extension Version 1.0, working as a coprocessor to CORE-V's CVA6 …
  ☆422Updated 2 weeks ago
• IntelLabs / riscv-vector
  Vector Acceleration IP core for RISC-V*
  ☆177Updated 2 weeks ago
• RV-BOSC / OpenNoC
  ☆152Updated last week
• openhwgroup / cv32e40x
  4 stage, in-order, compute RISC-V core based on the CV32E40P
  ☆235Updated 6 months ago
• ccelio / chisel-style-guide
  A Style Guide for the Chisel Hardware Construction Language
  ☆107Updated 3 years ago
• OpenXiangShan / HuanCun
  Open-source high-performance non-blocking cache
  ☆80Updated 2 weeks ago
• ucb-bar / riscv-mini
  Simple RISC-V 3-stage Pipeline in Chisel
  ☆572Updated 9 months ago
• chipsalliance / Cores-VeeR-EH2
  ☆232Updated 2 years ago
• ic-lab-duth / RISC-V-Vector
  Vector processor for RISC-V vector ISA
  ☆117Updated 4 years ago
• RoaLogic / RV12
  RISC-V CPU Core
  ☆324Updated 11 months ago