ucb-bar / chiseltestLinks
The batteries-included testing and formal verification library for Chisel-based RTL designs.
☆232Updated last year
Alternatives and similar repositories for chiseltest
Users that are interested in chiseltest are comparing it to the libraries listed below
Sorting:
- A Library of Chisel3 Tools for Digital Signal Processing☆242Updated last year
- Chisel examples and code snippets☆263Updated 3 years ago
- ☆359Updated 3 months ago
- A dynamic verification library for Chisel.☆159Updated last year
- A Chisel RTL generator for network-on-chip interconnects☆223Updated last month
- Provides various testers for chisel users☆100Updated 2 years ago
- Provides dot visualizations of chisel/firrtl circuits☆122Updated 2 years ago
- RISC-V Torture Test☆204Updated last year
- Lab exercises for Chisel in the digital electronics 2 course at DTU☆217Updated last month
- Verilog Configurable Cache☆187Updated 3 weeks ago
- Open source high performance IEEE-754 floating unit☆87Updated last year
- A Style Guide for the Chisel Hardware Construction Language☆108Updated 4 years ago
- Vector processor for RISC-V vector ISA☆133Updated 5 years ago
- Chisel Learning Journey☆111Updated 2 years ago
- Wrapper for Rocket-Chip on FPGAs☆138Updated 3 years ago
- Chisel/Firrtl execution engine☆153Updated last year
- Instruction Set Generator initially contributed by Futurewei☆302Updated 2 years ago
- Microarchitecture implementation of the decoupled vector-fetch accelerator☆160Updated last year
- VeeR EL2 Core☆309Updated this week
- A Fast, Low-Overhead On-chip Network☆255Updated last week
- A modular, parametrizable, and highly flexible Data Movement Accelerator (DMA)☆189Updated 3 months ago
- Open-source high-performance non-blocking cache☆92Updated 3 weeks ago
- SSRV(Super-Scalar RISC-V) --- Super-scalar out-of-order RV32IMC CPU core, 6.4 CoreMark/MHz.☆221Updated 5 years ago
- (System)Verilog to Chisel translator☆117Updated 3 years ago
- ☆301Updated last month
- Comment on the rocket-chip source code☆179Updated 7 years ago
- Parametric floating-point unit with support for standard RISC-V formats and operations as well as transprecision formats.☆549Updated 2 months ago
- Network on Chip Implementation written in SytemVerilog☆196Updated 3 years ago
- ☆190Updated 2 years ago
- Tile based architecture designed for computing efficiency, scalability and generality☆275Updated 3 months ago