Alternatives and similar repositories for ysyx-summer-readings

Users that are interested in ysyx-summer-readings are comparing it to the libraries listed below

• arch-simulator-sig / advanced-computer-architecture
  体系结构研讨 + ysyx高阶大纲 (WIP
  ☆191Updated last year
• OSCPU / yosys-sta
  ☆87Updated last month
• OSCPU / ysyxSoC
  ☆91Updated 2 months ago
• FurryAcetylCoA / gtkwave-filter-process-RISC
  A tool to decode RISC-V and LoongArch and MIPS instructions in gtkwave
  ☆31Updated 8 months ago
• OSCPU / chisel-playground
  ☆68Updated 10 months ago
• CmdBlockZQG / rvcore-mini-linux
  Build mini linux for your own RISC-V emulator!
  ☆24Updated last year
• tastynoob / aura-core
  "aura" my super-scalar O3 cpu core
  ☆24Updated last year
• OSCPU-Zhoushan / Zhoushan
  Open Source Chip Project by University (OSCPU) - Zhoushan Core
  ☆54Updated 3 years ago
• Yawei-Ding / ysyx_riscv64_cpu
  ☆72Updated 2 years ago
• OpenXiangShan / XiangShan-Design-Doc
  Documentation for XiangShan Design
  ☆37Updated 2 months ago
• puckbee / moli
  ☆35Updated 5 months ago
• OSCPU / ysyx-workbench
  ☆159Updated 3 weeks ago
• Groupsun / riscv-mini-five-stage
  This is my graduation project, a simple processor soft core, which implements RV32I ISA.
  ☆16Updated 6 years ago
• MrAMS / verilogModuleAddPrefix
  verilog module add prefix script 可用于ysyx项目添加学号
  ☆13Updated last year
• XS-MLVP / picker
  Pick your favorite language to verify your chip.
  ☆73Updated 2 weeks ago
• SocialistDalao / UltraMIPS_NSCSCC
  UltraMIPS SoC composed of dual-issue cpu, pipeline Cache and systematic peripheral.
  ☆145Updated last year
• Jpz-sdju / trinity
  ☆32Updated 4 months ago
• OpenXiangShan / GEM5
  ☆117Updated this week
• github-3rr0r / RV32ISC
  A RISC-V RV32I ISA Single Cycle CPU
  ☆25Updated 7 months ago
• schoeberl / chisel-lab
  Lab exercises for Chisel in the digital electronics 2 course at DTU
  ☆217Updated last month
• Clo91eaf / PUA-MIPS
  NSCSCC 2023 The Second Prize. TEAM PUA FROM HDU.
  ☆13Updated 8 months ago
• fluctlight001 / Generic-Cache-Module
  适用于龙芯杯团队赛入门选手的应急cache模块
  ☆31Updated last year
• OpenXiangShan / difftest
  Modern co-simulation framework for RISC-V CPUs
  ☆165Updated this week
• lshpku / hwd-prefetch-study
  A Study of the SiFive Inclusive L2 Cache
  ☆69Updated last year
• ysyx-ta / ysyx-slides
  ☆30Updated 6 months ago
• ftppz / ShanghaiTech-YSYX
  Unofficial guide for ysyx students applying to ShanghaiTech University
  ☆23Updated 9 months ago
• OSCPU / ysyx
  一生一芯的信息发布和内容网站
  ☆135Updated 2 years ago
• OpenXiangShan / gsim
  ☆63Updated 2 months ago
• fluctlight001 / cpu_for_nscscc2020
  2020龙芯杯个人赛 简易双发射60M（含ibuffer）
  ☆41Updated 5 years ago
• cyyself / soc-simulator
  A Verilator based SoC simulator that allows you to define AXI Slave interface in software.
  ☆50Updated 2 months ago