meow-chip / MeowV64Links
A superscalar RISC-V CPU with out-of-order execution and multi-core support
☆62Updated 3 years ago
Alternatives and similar repositories for MeowV64
Users that are interested in MeowV64 are comparing it to the libraries listed below
Sorting:
- A RISC-V core running Debian (and a LoongArch core running Linux).☆22Updated last year
- Linux-capable in-order superscaler LoongArch32r processor. Silicon-proven.☆42Updated 11 months ago
- ☆17Updated 3 years ago
- Run Rocket Chip on VCU128☆30Updated 7 months ago
- ☆33Updated 3 months ago
- Implements kernels with RISC-V Vector☆22Updated 2 years ago
- chipyard in mill :P☆78Updated last year
- Hardware design with Chisel☆33Updated 2 years ago
- A Verilator based SoC simulator that allows you to define AXI Slave interface in software.☆49Updated 8 months ago
- Open-source RISC-V cryptographic hardware token, RTL repo☆19Updated 2 years ago
- The 'missing header' for Chisel☆20Updated 3 months ago
- Lower chisel memories to SRAM macros☆12Updated last year
- Wrappers for open source FPU hardware implementations.☆32Updated last year
- CQU Dual Issue Machine☆35Updated last year
- Open-source high-performance non-blocking cache☆86Updated last month
- ☆40Updated last month
- A prototype GUI for chisel-development☆52Updated 5 years ago
- A simple OoO processor developed by njuallen and wierton, it won 2nd prize in LoongsonCup18.☆28Updated 5 years ago
- 第一届 RISC-V 中国峰会的幻灯片等资料存放☆37Updated 2 years ago
- Microarchitecture diagrams of several CPUs☆37Updated last week
- Dockerfile with Vivado for CI☆28Updated 5 years ago
- An SoC with multiple RISC-V IMA processors.☆19Updated 6 years ago
- ☆39Updated this week
- Open source high performance IEEE-754 floating unit☆77Updated last year
- A eDSL framework based on Scala and MLIR, focusing on the Hardware design.☆39Updated this week
- nscscc2018☆26Updated 6 years ago
- A Simple As Possible RISCV-32I core with debug module.☆42Updated 5 years ago
- Open-source non-blocking L2 cache☆43Updated this week
- RISC-V Vector (RVV) Automatic Tests Generator with full instructions coverage, including self-checking test and signature test (RISC-V Co…☆16Updated last year
- IOMMU IP compliant with the RISC-V IOMMU Specification v1.0☆96Updated this week