Alternatives and similar repositories for MeowV64:

Users that are interested in MeowV64 are comparing it to the libraries listed below

• sequencer / arithmetic
  ☆32Updated this week
• LainChip / LainCore
  Linux-capable in-order superscaler LoongArch32r processor. Silicon-proven.
  ☆38Updated 6 months ago
• Tang-Haojin / YuQuan
  A RISC-V core running Debian (and a LoongArch core running Linux).
  ☆22Updated 11 months ago
• jiegec / rvv-kernels
  Implements kernels with RISC-V Vector
  ☆21Updated last year
• OpenRigil / openrigil-rtl
  Open-source RISC-V cryptographic hardware token, RTL repo
  ☆19Updated 2 years ago
• cnyangkun / nscscc2018
  nscscc2018
  ☆26Updated 6 years ago
• cyyself / soc-simulator
  A Verilator based SoC simulator that allows you to define AXI Slave interface in software.
  ☆46Updated 3 months ago
• ljwljwljwljw / DiplomaticBackend
  ☆17Updated 2 years ago
• sequencer / zaozi
  The experimental work to rewrite Chisel in pure Scala 3 and the Panama Project
  ☆24Updated this week
• jiegec / rocket-chip-vcu128
  Run Rocket Chip on VCU128
  ☆29Updated 2 months ago
• redpanda3 / chisel-book
  Hardware design with Chisel
  ☆31Updated 2 years ago
• jiegec / fpu-wrappers
  Wrappers for open source FPU hardware implementations.
  ☆30Updated 10 months ago
• chipsalliance / playground
  chipyard in mill :P
  ☆77Updated last year
• jiegec / chisel-memory-lower
  Lower chisel memories to SRAM macros
  ☆12Updated 10 months ago
• riscv-and-rust-and-decaf / riscv32i-cpu-chisel
  riscv32i-cpu
  ☆19Updated 4 years ago
• watz0n / learn-rv32i-asap
  A Simple As Possible RISCV-32I core with debug module.
  ☆42Updated 5 years ago
• chipsalliance / chisel-interface
  The 'missing header' for Chisel
  ☆18Updated this week
• OpenXiangShan / HuanCun
  Open-source high-performance non-blocking cache
  ☆75Updated this week
• mollybuild / RISCV-Measurement
  This is a repo for recording and reporting RISCV platform's test and measurement continuously.
  ☆57Updated last year
• cnrv / RVWC2021-slides
  第一届 RISC-V 中国峰会的幻灯片等资料存放
  ☆37Updated 2 years ago
• nju-mips / noop-lo
  A simple OoO processor developed by njuallen and wierton, it won 2nd prize in LoongsonCup18.
  ☆26Updated 5 years ago
• riscv / riscv-aclint
  ☆42Updated 3 years ago
• Superscalar-HIT-Core / Superscalar-HIT-Core-NSCSCC2020
  a Quad-issue, Out-of-order Superscalar MIPS Processor Implemented in SystemVerilog
  ☆46Updated last year
• josecm / riscv-hyp-tests
  A bare-metal application to test specific features of the risc-v hypervisor extension
  ☆36Updated last year
• ucb-bar / chisel-gui
  A prototype GUI for chisel-development
  ☆52Updated 4 years ago
• chipsalliance / espresso
  ☆37Updated last year
• jiegec / kb
  My knowledge base
  ☆42Updated last week
• thu-cs-lab / JieLabs-Web
  Backend & Frontend for JieLabs
  ☆22Updated last year
• OpenXiangShan / CoupledL2
  Open-source non-blocking L2 cache
  ☆35Updated this week
• jiegec / verilog-lang
  A hand-written recursive decent Verilog parser.
  ☆11Updated 2 years ago