Alternatives and similar repositories for MeowV64

Users that are interested in MeowV64 are comparing it to the libraries listed below

• LainChip / LainCore
  Linux-capable in-order superscaler LoongArch32r processor. Silicon-proven.
  ☆45Updated last year
• jiegec / fpu-wrappers
  Wrappers for open source FPU hardware implementations.
  ☆35Updated last year
• jiegec / rocket-chip-vcu128
  Run Rocket Chip on VCU128
  ☆30Updated 3 weeks ago
• chipsalliance / playground
  chipyard in mill :P
  ☆77Updated last year
• jiegec / rvv-kernels
  Implements kernels with RISC-V Vector
  ☆22Updated 2 years ago
• Tang-Haojin / YuQuan
  A RISC-V core running Debian (and a LoongArch core running Linux).
  ☆22Updated last week
• cyyself / soc-simulator
  A Verilator based SoC simulator that allows you to define AXI Slave interface in software.
  ☆49Updated last month
• sequencer / arithmetic
  ☆33Updated 7 months ago
• ljwljwljwljw / DiplomaticBackend
  ☆17Updated 3 years ago
• cnrv / RVWC2021-slides
  第一届 RISC-V 中国峰会的幻灯片等资料存放
  ☆38Updated 2 years ago
• chipsalliance / chisel-interface
  The 'missing header' for Chisel
  ☆21Updated 7 months ago
• redpanda3 / chisel-book
  Hardware design with Chisel
  ☆35Updated 2 years ago
• OpenXiangShan / HuanCun
  Open-source high-performance non-blocking cache
  ☆91Updated this week
• Maxpicca-Li / CDIM
  CQU Dual Issue Machine
  ☆37Updated last year
• OpenXiangShan / CoupledL2
  Open-source non-blocking L2 cache
  ☆50Updated this week
• OpenXiangShan / fudian
  Open source high performance IEEE-754 floating unit
  ☆86Updated last year
• OpenRigil / openrigil-rtl
  Open-source RISC-V cryptographic hardware token, RTL repo
  ☆20Updated 3 years ago
• jiegec / kb
  My knowledge base
  ☆72Updated last week
• jiegec / chisel-memory-lower
  Lower chisel memories to SRAM macros
  ☆12Updated last year
• ucb-bar / chisel-gui
  A prototype GUI for chisel-development
  ☆51Updated 5 years ago
• cyyself / cyyrv64
  My RV64 CPU (Work in progress)
  ☆19Updated 2 years ago
• riscv / riscv-control-transfer-records
  This repo contains a RISC-V ISA extension (proposal) to allow recording of control transfer history to on-chip registers, to support usag…
  ☆23Updated 8 months ago
• watz0n / learn-rv32i-asap
  A Simple As Possible RISCV-32I core with debug module.
  ☆42Updated 5 years ago
• nju-mips / noop-lo
  A simple OoO processor developed by njuallen and wierton, it won 2nd prize in LoongsonCup18.
  ☆30Updated 5 years ago
• chipsalliance / espresso
  ☆41Updated 5 months ago
• jiegec / cpu
  Microarchitecture diagrams of several CPUs
  ☆43Updated last month
• litmus-tests / litmus-tests-riscv
  RISC-V architecture concurrency model litmus tests
  ☆92Updated 5 months ago
• NSCSCC-2022-TJU / ChiselMIPS
  第六届龙芯杯混元形意太极门战队作品
  ☆18Updated 3 years ago
• XS-MLVP / UnityChipForXiangShan
  Crowdsourced Verification Project (UnityChip Verification) for the Xiangshan Processor
  ☆45Updated 2 weeks ago
• char-fish-after-lunch / SystemOnCat
  An SoC with multiple RISC-V IMA processors.
  ☆19Updated 7 years ago