Alternatives and similar repositories for EasyDiff-noop

Users that are interested in EasyDiff-noop are comparing it to the libraries listed below

• ljwljwljwljw / DiplomaticBackend
  ☆17Updated 3 years ago
• sequencer / arithmetic
  ☆33Updated last month
• msyksphinz-self / riscv-vector-tests
  Original test vector of RISC-V Vector Extension
  ☆11Updated 4 years ago
• xunqianxun / liguoqi-rv64-cpu
  RISC-V 64 CPU
  ☆10Updated 2 years ago
• lizhirui / DreamCoreV2
  ☆22Updated 2 years ago
• chipsalliance / tilelink
  ☆30Updated 5 months ago
• jiegec / rocket-chip-vcu128
  Run Rocket Chip on VCU128
  ☆30Updated 5 months ago
• whutddk / RiftCore
  RiftCore is a 9-stage, single-issue, out-of-order 64-bits RISC-V Core, which supports RV64IMC and 3-level Cache System
  ☆41Updated 2 years ago
• shinezyy / gem5_data_proc
  data preprocessing scripts for gem5 output
  ☆18Updated 4 months ago
• SchaffHub / RISC-Verdi
  Synopsys Verdi applet that presents a view of the source code running on a RISC-V processor with a simulation waveform.
  ☆30Updated 5 years ago
• Tang-Haojin / YuQuan
  A RISC-V core running Debian (and a LoongArch core running Linux).
  ☆22Updated last year
• CherrySprings / CherrySprings
  ☆18Updated 2 years ago
• lingscale / cc01
  ☆31Updated 2 months ago
• Superscalar-HIT-Core / Superscalar-HIT-Core-NSCSCC2020
  a Quad-issue, Out-of-order Superscalar MIPS Processor Implemented in SystemVerilog
  ☆47Updated last year
• riscv-boom / riscv-coremark
  Setup scripts and files needed to compile CoreMark on RISC-V
  ☆65Updated 9 months ago
• ved-rivos / iommu-rtl
  RISC-V IOMMU in verilog
  ☆17Updated 2 years ago
• anycore / anycore-riscv-src
  The RTL source for AnyCore RISC-V
  ☆32Updated 3 years ago
• zero-day-labs / riscv-aia
  AIA IP compliant with the RISC-V AIA spec
  ☆40Updated 3 months ago
• comparch-security / spike-cache
  Spike with a coherence supported cache model
  ☆13Updated 10 months ago
• tastynoob / aura-core
  "aura" my super-scalar O3 cpu core
  ☆24Updated 11 months ago
• OpenXiangShan / Deterload
  Xiangshan deterministic workloads generator
  ☆18Updated 2 months ago
• josecm / riscv-hyp-tests
  A bare-metal application to test specific features of the risc-v hypervisor extension
  ☆40Updated last year
• cnrv / clone-helpers
  Helper scripts used to clone RISC-V related git repos inside China.
  ☆15Updated 4 years ago
• cassuto / nano-cpu32k
  Linux-capable superscalar out-of-order RISC core (with Cache& MMU) and SoC, having been verified on Xilinx Kintex-7 FPGA.
  ☆54Updated 8 months ago
• msyksphinz-self / minimal-diplomacy
  Example of Chisel3 Diplomacy
  ☆11Updated 3 years ago
• OSCPU / chisel-playground
  ☆67Updated 3 months ago
• nju-mips / noop-lo
  A simple OoO processor developed by njuallen and wierton, it won 2nd prize in LoongsonCup18.
  ☆28Updated 5 years ago
• carrv / carrv.github.io
  Workshop on Computer Architecture Research with RISC-V (CARRV)
  ☆39Updated 6 months ago
• RPTU-EIS / RISCV-Core
  5-stage RISC-V core (RV32IM) with pipelining designed for educational purposes by RPTU Kaiserslautern, Germany
  ☆12Updated 10 months ago
• riscv-verification / riscvISACOV
  SystemVerilog Functional Coverage for RISC-V ISA
  ☆28Updated 7 months ago