Super fast RISC-V ISA emulator for XiangShan processor
☆334Jul 2, 2026Updated this week
Alternatives and similar repositories for NEMU
Users that are interested in NEMU are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- Modern co-simulation framework for RISC-V CPUs☆181Jun 27, 2026Updated last week
- ☆43Jun 25, 2026Updated last week
- NJU EMUlator, a full system x86/mips32/riscv32/riscv64 emulator for teaching☆1,113Nov 14, 2025Updated 7 months ago
- Open-source high-performance non-blocking cache☆99Jun 17, 2026Updated 2 weeks ago
- ☆147Updated this week
- Managed Database hosting by DigitalOcean • AdPostgreSQL, MySQL, MongoDB, Kafka, Valkey, and OpenSearch available. Automatically scale up storage and focus on building your apps.
- Open-source non-blocking L2 cache☆63Jun 26, 2026Updated last week
- Open-source high-performance RISC-V processor☆7,106Updated this week
- LLCL-MIPS is a superscalar MIPS processor, which supports MIPS Release 1 instructions and is capable of booting linux kernel. (第五届龙芯杯特等奖作…☆41Jan 26, 2022Updated 4 years ago
- A binary instrumentation tool to analyze load instructions in any off-the-shelf x86(-64) program. Described by Bera et al. in https://arx…☆24Jun 30, 2024Updated 2 years ago
- RISC-V SoC designed by students in UCAS☆1,534Jun 5, 2026Updated 3 weeks ago
- XiangShan Frontend Develop Environment☆72Jun 26, 2026Updated last week
- ☆95Apr 14, 2026Updated 2 months ago
- Documentation for XiangShan☆442Jun 24, 2026Updated last week
- ☆14Apr 28, 2026Updated 2 months ago
- 1-Click AI Models by DigitalOcean Gradient • AdDeploy popular AI models on DigitalOcean Gradient GPU virtual machines with just a single click. Zero configuration with optimized deployments.
- A minimal, modularized, and machine-independent hardware abstraction layer☆536May 1, 2026Updated 2 months ago
- A RISC-V core running Debian (and a LoongArch core running Linux).☆23Nov 24, 2025Updated 7 months ago
- Spike, a RISC-V ISA Simulator☆3,154Jun 26, 2026Updated last week
- How to make undergraduates or new graduates ready for advanced computer architecture research or modern CPU design☆659Aug 13, 2024Updated last year
- RISC-V Open Source Supervisor Binary Interface☆1,491Jun 17, 2026Updated 2 weeks ago
- GPGPU processor supporting RISCV-V extension, developed with Chisel HDL☆922Jun 27, 2026Updated last week
- A simple full system emulator. Currently support RV64IMACSU and MIPS32 and LoongArch32. Capable of booting Linux. Suitable for education …☆121Oct 31, 2024Updated last year
- Paging Debug tool for GDB using python☆13Jun 4, 2022Updated 4 years ago
- ☆12Jan 19, 2022Updated 4 years ago
- Wordpress hosting with auto-scaling - Free Trial Offer • AdFully Managed hosting for WordPress and WooCommerce businesses that need reliable, auto-scalable performance. Cloudways SafeUpdates now available.
- The official repository for the gem5 computer-system architecture simulator.☆2,674Jun 26, 2026Updated last week
- A eDSL framework based on Scala and MLIR, focusing on the Hardware design.☆73Jun 27, 2026Updated last week
- ☆22Nov 25, 2023Updated 2 years ago
- Our repository for NSCSCC☆21Feb 22, 2025Updated last year
- 给NEMU移植Linux Kernel!☆23Jun 1, 2025Updated last year
- Fuxi (伏羲) is a 32-bit pipelined RISC-V processor written in Chisel3.☆183Jun 28, 2021Updated 5 years ago
- RustSBI support on SiFive FU740 board; FU740 is a five-core heterogeneous processor with four SiFive U74 cores, and one SiFive S7 core☆17Jul 20, 2023Updated 2 years ago
- Unit tests generator for RVV 1.0☆114May 25, 2026Updated last month
- ☆17Mar 17, 2022Updated 4 years ago
- Deploy to Railway using AI coding agents - Free Credits Offer • AdUse Claude Code, Codex, OpenCode, and more. Autonomous software development now has the infrastructure to match with Railway.
- A simple MIPS CPU for BUAA CO course (and now NSCSCC).☆10May 15, 2021Updated 5 years ago
- ☆75Jun 13, 2026Updated 3 weeks ago
- GNU toolchain for RISC-V, including GCC☆4,543Jun 6, 2026Updated 3 weeks ago
- High performance LA32R out-of-order processor core. (NSCSCC 2023 Special Prize)☆92Aug 29, 2023Updated 2 years ago
- A simple and fast RISC-V JIT emulator.☆160Aug 21, 2024Updated last year
- SonicBOOM: The Berkeley Out-of-Order Machine☆2,186Jun 26, 2026Updated last week
- A RISC-V ELF psABI Document☆848Jun 18, 2026Updated 2 weeks ago