Alternatives and similar repositories for NEMU:

Users that are interested in NEMU are comparing it to the libraries listed below

• OpenXiangShan / difftest
  Modern co-simulation framework for RISC-V CPUs
  ☆139Updated last week
• arch-simulator-sig / advanced-computer-architecture
  体系结构研讨 + ysyx高阶大纲 (WIP
  ☆150Updated 6 months ago
• OSCPU / NutShell-doc
  ☆122Updated 2 years ago
• OpenXiangShan / XiangShan-doc
  Documentation for XiangShan
  ☆410Updated last week
• plctlab / writing-your-first-riscv-simulator
  《从零开始的RISC-V模拟器开发》配套的PPT和教学资料
  ☆217Updated 3 years ago
• NJU-ProjectN / nvboard
  NJU Virtual Board
  ☆269Updated 3 months ago
• OSCPU / ysyx-workbench
  ☆144Updated 7 months ago
• DawnCarol / DawnCarol
  ☆186Updated this week
• shinezyy / micro-arch-training
  How to make undergraduates or new graduates ready for advanced computer architecture research or modern CPU design
  ☆551Updated 8 months ago
• MaxXSoft / Fuxi
  Fuxi (伏羲) is a 32-bit pipelined RISC-V processor written in Chisel3.
  ☆173Updated 3 years ago
• LoveLonelyTime / Bergamot
  An exquisite superscalar RV32GC processor.
  ☆155Updated 3 months ago
• hehao98 / RISCV-Simulator
  A Simple RISC-V CPU Simulator with 5 Stage Pipeline, Branch Prediction and Cache Simulation
  ☆182Updated last year
• THU-DSP-LAB / ventus-gpgpu
  GPGPU processor supporting RISCV-V extension, developed with Chisel HDL
  ☆722Updated this week
• USTC-System-Courses / CECS-Lab
  ☆35Updated last year
• Lingrui98 / RISC-V-book
  A translation project of the RISC-V reader
  ☆175Updated last year
• plctlab / llvm-project
  PLCT实验室的 RISC-V V Spec 实现，基于llvm/llvm-project，rkruppe/rvv-llvm 和 https://repo.hca.bsc.es/gitlab/rferrer/llvm-epi-0.8
  ☆160Updated 4 months ago
• kaitoukito / A-Primer-on-Memory-Consistency-and-Cache-Coherence
  A Primer on Memory Consistency and Cache Coherence (Second Edition) 翻译计划
  ☆225Updated 11 months ago
• OSCPU-Zhoushan / Zhoushan
  Open Source Chip Project by University (OSCPU) - Zhoushan Core
  ☆50Updated 2 years ago
• OpenXiangShan / GEM5
  ☆77Updated this week
• ucb-bar / riscv-mini
  Simple RISC-V 3-stage Pipeline in Chisel
  ☆569Updated 8 months ago
• OSCPU / ysyx
  一生一芯的信息发布和内容网站
  ☆130Updated last year
• OpenXiangShan / xs-env
  XiangShan Frontend Develop Environment
  ☆55Updated 2 weeks ago
• skyzh / RISCV-Simulator
  💻 RISC-V Simulator of RV32I ISA. 5-stage pipeline / out-of-order execution with Tomasulo algorithm and Speculation. Support runtime visu…
  ☆201Updated 4 years ago
• f0rm2l1n / riscv-simulator-guide
  RISC-V模拟器，相关硬件实现`riscv-isa-sim`以及模拟器pk, bbl的指导手册
  ☆52Updated 5 years ago
• Evensgn / RISC-V-CPU
  RISC-V CPU with 5-stage pipeline, implemented in Verilog HDL.
  ☆270Updated 7 years ago
• ISRC-CAS / riscv-isa-manual-cn
  ☆152Updated last year
• runninglinuxkernel / riscv_programming_practice
  ☆203Updated last year
• openhwgroup / force-riscv
  Instruction Set Generator initially contributed by Futurewei
  ☆275Updated last year
• cnrv / riscv-soc-book
  关于RISC-V你所需要知道的一切
  ☆556Updated 2 years ago
• schoeberl / chisel-lab
  Lab exercises for Chisel in the digital electronics 2 course at DTU
  ☆194Updated 3 weeks ago