nju-mips / noop-lo
A simple OoO processor developed by njuallen and wierton, it won 2nd prize in LoongsonCup18.
☆28Updated 5 years ago
Alternatives and similar repositories for noop-lo:
Users that are interested in noop-lo are comparing it to the libraries listed below
- ☆33Updated last month
- An open source SDR SDRAM controller based on the AXI4 bus and verified by FPGA and tapeout. It can support memory particles of different …☆17Updated last month
- ☆30Updated 5 months ago
- A series of RISC-V soft core processor written from scratch. Now, we're using all open-source toolchain (chisel, mill, verilator, NEMU, …☆39Updated last year
- Open-source AMBA CHI infrastructures (supporting Issue B, E.b)☆18Updated last week
- Setup scripts and files needed to compile CoreMark on RISC-V☆65Updated 9 months ago
- StateMover is a checkpoint-based debugging framework for FPGAs.☆19Updated 2 years ago
- RISC-V模拟器,相关硬件实现`riscv-isa-sim`以及模拟器pk, bbl的指导手册☆52Updated 5 years ago
- A bare-metal application to test specific features of the risc-v hypervisor extension☆39Updated last year
- The official NaplesPU hardware code repository☆16Updated 5 years ago
- ☆17Updated 3 years ago
- Example of Chisel3 Diplomacy☆11Updated 3 years ago
- Pick your favorite language to verify your chip.☆49Updated this week
- ☆27Updated 4 years ago
- The 'missing header' for Chisel☆20Updated last month
- An almost empty chisel project as a starting point for hardware design☆30Updated 3 months ago
- A RISC-V core running Debian (and a LoongArch core running Linux).☆22Updated last year
- 5-stage RISC-V core (RV32IM) with pipelining designed for educational purposes by RPTU Kaiserslautern, Germany☆12Updated 9 months ago
- Transactional Verilog design and Verilator Testbench for a RISC-V TensorCore Vector co-processor for reproducible linear algebra☆53Updated 3 years ago
- Run Rocket Chip on VCU128☆30Updated 5 months ago
- A superscalar RISC-V CPU with out-of-order execution and multi-core support☆62Updated 3 years ago
- HW-SW Co-Simulation Library for AMBA AXI BFM using DPI/VPI☆31Updated 4 months ago
- RiftCore is a 9-stage, single-issue, out-of-order 64-bits RISC-V Core, which supports RV64IMC and 3-level Cache System☆41Updated 2 years ago
- DUTH RISC-V Superscalar Microprocessor☆31Updated 6 months ago
- ☆31Updated last month
- This repo includes XiangShan's function units☆21Updated last week
- SystemVerilog implemention of the TAGE branch predictor☆12Updated 3 years ago
- ☆27Updated 3 weeks ago
- vector multiplication adder accelerator (using chisel 3 and RocketChip RoCC ) 向量乘法累加加速器☆52Updated 5 years ago
- The RTL source for AnyCore RISC-V☆32Updated 3 years ago