Alternatives and similar repositories for soc-simulator:

Users that are interested in soc-simulator are comparing it to the libraries listed below

• FurryAcetylCoA / gtkwave-filter-process-RISC
  A tool to decode RISC-V and LoongArch and MIPS instructions in gtkwave
  ☆28Updated 10 months ago
• Tang-Haojin / YuQuan
  A RISC-V core running Debian (and a LoongArch core running Linux).
  ☆22Updated 11 months ago
• cyyself / cemu
  A simple full system emulator. Currently support RV64IMACSU and MIPS32 and LoongArch32. Capable of booting Linux. Suitable for education …
  ☆111Updated 3 months ago
• Clo91eaf / PUA-MIPS
  NSCSCC 2023 The Second Prize. TEAM PUA FROM HDU.
  ☆10Updated 10 months ago
• OSCPU / chisel-playground
  ☆59Updated last week
• Maxpicca-Li / CDIM
  CQU Dual Issue Machine
  ☆35Updated 7 months ago
• ftppz / ShanghaiTech-YSYX
  Unofficial guide for ysyx students applying to ShanghaiTech University
  ☆20Updated 7 months ago
• tastynoob / aura-core
  "aura" my super-scalar O3 cpu core
  ☆24Updated 8 months ago
• zencove-thu / zencove-zoom
  Highly configurable out-of-order MIPS32 processor, capable of booting Linux.
  ☆38Updated last year
• MaZirui2001 / Zircon
  ☆23Updated 3 weeks ago
• HIT-MaRiver-mips / cpucore-mariver
  ☆32Updated last year
• OSCPU / ysyxSoC
  ☆79Updated this week
• OSCPU / yosys-sta
  ☆53Updated last month
• fluctlight001 / Generic-Cache-Module
  适用于龙芯杯团队赛入门选手的应急cache模块
  ☆21Updated 11 months ago
• NOP-Processor / NOP-Core
  High performance LA32R out-of-order processor core. (NSCSCC 2023 Special Prize)
  ☆74Updated last year
• OSCPU-Zhoushan / Zhoushan
  Open Source Chip Project by University (OSCPU) - Zhoushan Core
  ☆47Updated 2 years ago
• Superscalar-HIT-Core / Superscalar-HIT-Core-NSCSCC2020
  a Quad-issue, Out-of-order Superscalar MIPS Processor Implemented in SystemVerilog
  ☆46Updated last year
• nscscc2019ucas / nscscc2019ucas
  ☆33Updated 5 years ago
• LainChip / LainCore
  Linux-capable in-order superscaler LoongArch32r processor. Silicon-proven.
  ☆38Updated 6 months ago
• NSCSCC-2022-TJU / ChiselMIPS
  第六届龙芯杯混元形意太极门战队作品
  ☆17Updated 2 years ago
• ysyx-ta / ysyx-summer-readings
  ☆61Updated 6 months ago
• chipsalliance / rvdecoderdb
  The Scala parser to parse riscv/riscv-opcodes generate
  ☆13Updated last week
• MrAMS / verilogModuleAddPrefix
  verilog module add prefix script 可用于ysyx项目添加学号
  ☆13Updated 11 months ago
• Tanggling / BOOMCore
  This is a project created and completed by team BOOM(Beihang OO masters).This is a superscalar processor with a 13-stage out-of-order dua…
  ☆14Updated 4 months ago
• name1e5s / Sirius
  Asymmetric dual issue in-order microprocessor.
  ☆34Updated 5 years ago
• OSCPU / openperf
  ☆11Updated this week
• iFuProcessor / iFuCore
  ☆15Updated 6 months ago
• huang-jl / LLCL-MIPS
  LLCL-MIPS is a superscalar MIPS processor, which supports MIPS Release 1 instructions and is capable of booting linux kernel. （第五届龙芯杯特等奖作…
  ☆34Updated 3 years ago
• OpenXiangShan / GEM5
  ☆74Updated this week