Alternatives and similar repositories for soc-simulator

Users that are interested in soc-simulator are comparing it to the libraries listed below

• Maxpicca-Li / CDIM
  CQU Dual Issue Machine
  ☆38Updated last year
• NOP-Processor / NOP-Core
  High performance LA32R out-of-order processor core. (NSCSCC 2023 Special Prize)
  ☆82Updated 2 years ago
• OSCPU / chisel-playground
  ☆68Updated 10 months ago
• zencove-thu / zencove-zoom
  Highly configurable out-of-order MIPS32 processor, capable of booting Linux.
  ☆40Updated 2 years ago
• cyyself / cemu
  A simple full system emulator. Currently support RV64IMACSU and MIPS32 and LoongArch32. Capable of booting Linux. Suitable for education …
  ☆119Updated last year
• FurryAcetylCoA / gtkwave-filter-process-RISC
  A tool to decode RISC-V and LoongArch and MIPS instructions in gtkwave
  ☆31Updated 8 months ago
• ysyx-ta / ysyx-summer-readings
  ☆67Updated last year
• fluctlight001 / Generic-Cache-Module
  适用于龙芯杯团队赛入门选手的应急cache模块
  ☆31Updated last year
• Superscalar-HIT-Core / Superscalar-HIT-Core-NSCSCC2020
  a Quad-issue, Out-of-order Superscalar MIPS Processor Implemented in SystemVerilog
  ☆50Updated 2 years ago
• Clo91eaf / PUA-MIPS
  NSCSCC 2023 The Second Prize. TEAM PUA FROM HDU.
  ☆13Updated 8 months ago
• OpenXiangShan / XiangShan-Design-Doc
  Documentation for XiangShan Design
  ☆37Updated 2 months ago
• Tang-Haojin / YuQuan
  A RISC-V core running Debian (and a LoongArch core running Linux).
  ☆22Updated last month
• tastynoob / aura-core
  "aura" my super-scalar O3 cpu core
  ☆24Updated last year
• OSCPU / ysyxSoC
  ☆91Updated 2 months ago
• OpenXiangShan / gsim
  ☆64Updated 2 months ago
• OSCPU-Zhoushan / Zhoushan
  Open Source Chip Project by University (OSCPU) - Zhoushan Core
  ☆54Updated 3 years ago
• OSCPU / yosys-sta
  ☆89Updated last month
• gmlayer0 / wired
  Linux-capable out-of-order superscaler multicore LoongArch32 (LA32 / LA32R) processor.
  ☆32Updated last year
• iFuProcessor / iFuCore
  ☆20Updated last year
• OpenXiangShan / difftest
  Modern co-simulation framework for RISC-V CPUs
  ☆165Updated this week
• MAdrid1011 / Zircon
  ☆29Updated 11 months ago
• XS-MLVP / picker
  Pick your favorite language to verify your chip.
  ☆74Updated this week
• huang-jl / LLCL-MIPS
  LLCL-MIPS is a superscalar MIPS processor, which supports MIPS Release 1 instructions and is capable of booting linux kernel. （第五届龙芯杯特等奖作…
  ☆37Updated 3 years ago
• ftppz / ShanghaiTech-YSYX
  Unofficial guide for ysyx students applying to ShanghaiTech University
  ☆23Updated 10 months ago
• NSCSCC-2022-TJU / ChiselMIPS
  第六届龙芯杯混元形意太极门战队作品
  ☆18Updated 3 years ago
• LainChip / LainCore
  Linux-capable in-order superscaler LoongArch32r processor. Silicon-proven.
  ☆45Updated last year
• HIT-MaRiver-mips / cpucore-mariver
  ☆35Updated 2 years ago
• AlwenXXD / nscscc2021
  龙芯杯21个人赛作品
  ☆36Updated 4 years ago
• OpenXiangShan / GEM5
  ☆117Updated this week
• OpenXiangShan / Deterload
  Xiangshan deterministic workloads generator
  ☆24Updated 7 months ago