Alternatives and similar repositories for chisel-playground

Users that are interested in chisel-playground are comparing it to the libraries listed below

• OSCPU / yosys-sta
  ☆73Updated 2 months ago
• OSCPU / ysyxSoC
  ☆86Updated 2 months ago
• ysyx-ta / ysyx-summer-readings
  ☆66Updated 11 months ago
• OSCPU-Zhoushan / Zhoushan
  Open Source Chip Project by University (OSCPU) - Zhoushan Core
  ☆51Updated 2 years ago
• schoeberl / chisel-lab
  Lab exercises for Chisel in the digital electronics 2 course at DTU
  ☆204Updated last month
• OpenXiangShan / GEM5
  ☆88Updated this week
• tastynoob / aura-core
  "aura" my super-scalar O3 cpu core
  ☆24Updated last year
• XS-MLVP / picker
  Pick your favorite language to verify your chip.
  ☆51Updated this week
• OpenXiangShan / XiangShan-Design-Doc
  Documentation for XiangShan Design
  ☆29Updated this week
• FurryAcetylCoA / gtkwave-filter-process-RISC
  A tool to decode RISC-V and LoongArch and MIPS instructions in gtkwave
  ☆31Updated 3 months ago
• OpenXiangShan / difftest
  Modern co-simulation framework for RISC-V CPUs
  ☆147Updated this week
• arch-simulator-sig / advanced-computer-architecture
  体系结构研讨 + ysyx高阶大纲 (WIP
  ☆172Updated 8 months ago
• CherrySprings / CherrySprings
  ☆18Updated 2 years ago
• lizhirui / DreamCore
  ☆64Updated 2 years ago
• sycuricon / starship
  Run rocket-chip on FPGA
  ☆68Updated 8 months ago
• RV-BOSC / OpenNoC
  ☆168Updated 2 weeks ago
• schoeberl / chisel-examples
  Chisel examples and code snippets
  ☆255Updated 2 years ago
• microdynamics-cpu / tree-core-cpu
  A series of RISC-V soft core processor written from scratch. Now, we're using all open-source toolchain (chisel, mill, verilator, NEMU, …
  ☆41Updated last year
• sifferman / labs-with-cva6
  Advanced Architecture Labs with CVA6
  ☆65Updated last year
• ccelio / chisel-style-guide
  A Style Guide for the Chisel Hardware Construction Language
  ☆108Updated 3 years ago
• Intensivate / learning-journey
  Chisel Learning Journey
  ☆109Updated 2 years ago
• cyyself / soc-simulator
  A Verilator based SoC simulator that allows you to define AXI Slave interface in software.
  ☆49Updated 8 months ago
• OpenXiangShan / fudian
  Open source high performance IEEE-754 floating unit
  ☆77Updated last year
• cnrv / fpga-rocket-chip
  Wrapper for Rocket-Chip on FPGAs
  ☆135Updated 2 years ago
• Jpz-sdju / trinity
  ☆24Updated 3 months ago
• ucb-bar / constellation
  A Chisel RTL generator for network-on-chip interconnects
  ☆204Updated 2 months ago
• schoeberl / chisel-empty
  An almost empty chisel project as a starting point for hardware design
  ☆32Updated 5 months ago
• sequencer / arithmetic
  ☆33Updated 3 months ago
• chipsalliance / playground
  chipyard in mill :P
  ☆78Updated last year
• chipsalliance / riscv-vector-tests
  Unit tests generator for RVV 1.0
  ☆88Updated 2 months ago