OSCPU / chisel-playground

Related projects ⓘ

Alternatives and complementary repositories for chisel-playground

• OSCPU / ysyxSoC
  ☆76Updated 2 months ago
• OSCPU-Zhoushan / Zhoushan
  Open Source Chip Project by University (OSCPU) - Zhoushan Core
  ☆46Updated 2 years ago
• OpenXiangShan / difftest
  Modern co-simulation framework for RISC-V CPUs
  ☆116Updated this week
• RV-BOSC / OpenNoC
  ☆61Updated 2 months ago
• OSCPU / yosys-sta
  ☆41Updated 3 months ago
• lizhirui / DreamCore
  ☆63Updated 2 years ago
• arch-simulator-sig / advanced-computer-architecture
  体系结构研讨 + ysyx高阶大纲 (WIP
  ☆114Updated 3 weeks ago
• chipsalliance / t1
  ☆118Updated this week
• Tang-Haojin / YuQuan
  A RISC-V core running Debian (and a LoongArch core running Linux).
  ☆20Updated 8 months ago
• tastynoob / aura-core
  "aura" my super-scalar O3 cpu core
  ☆24Updated 5 months ago
• OpenXiangShan / GEM5
  ☆66Updated this week
• ysyx-ta / ysyx-summer-readings
  ☆59Updated 3 months ago
• FurryAcetylCoA / gtkwave-filter-process-RISC
  A tool to decode RISC-V and LoongArch and MIPS instructions in gtkwave
  ☆25Updated 7 months ago
• lizhirui / DreamCoreV2
  ☆20Updated last year
• XS-MLVP / picker
  Pick your favorite language to verify your chip.
  ☆30Updated 2 weeks ago
• sycuricon / starship
  Run rocket-chip on FPGA
  ☆60Updated 4 months ago
• sifive / block-inclusivecache-sifive
  ☆74Updated 2 years ago
• sequencer / arithmetic
  ☆31Updated last month
• CherrySprings / CherrySprings
  ☆17Updated last year
• chipsalliance / playground
  chipyard in mill :P
  ☆75Updated 11 months ago
• ccelio / chisel-style-guide
  A Style Guide for the Chisel Hardware Construction Language
  ☆106Updated 3 years ago
• schoeberl / chisel-lab
  Lab exercises for Chisel in the digital electronics 2 course at DTU
  ☆172Updated this week
• OpenXiangShan / XS-Verilog-Library
  ☆36Updated 2 years ago
• OpenXiangShan / xs-env
  XiangShan Frontend Develop Environment
  ☆45Updated last week
• lshpku / hwd-prefetch-study
  A Study of the SiFive Inclusive L2 Cache
  ☆43Updated 10 months ago
• cyyself / soc-simulator
  A Verilator based SoC simulator that allows you to define AXI Slave interface in software.
  ☆43Updated this week
• OpenXiangShan / fudian
  Open source high performance IEEE-754 floating unit
  ☆59Updated 8 months ago
• ucb-ucie / uciedigital
  Pure digital components of a UCIe controller
  ☆47Updated this week
• Chainsaw-Team / Chainsaw
  a hardware design library based on SpinalHDL, especially for stream processing operators on Xilinx FPGAs for Arithmetic, DSP, Communicati…
  ☆54Updated 10 months ago