ucb-bar / chisel-tutorialLinks
chisel tutorial exercises and answers
☆739Updated 3 years ago
Alternatives and similar repositories for chisel-tutorial
Users that are interested in chisel-tutorial are comparing it to the libraries listed below
Sorting:
- Generator Bootcamp Material: Learn Chisel the Right Way☆1,093Updated last year
- educational microarchitectures for risc-v isa☆727Updated 3 months ago
- Digital Design with Chisel☆882Updated 3 weeks ago
- A template project for beginning new Chisel work☆675Updated 2 months ago
- Simple RISC-V 3-stage Pipeline in Chisel☆602Updated last year
- Flexible Intermediate Representation for RTL☆749Updated last year
- CV32E40P is an in-order 4-stage RISC-V RV32IMFCXpulp CPU based on RI5CY from PULP-Platform☆1,152Updated 6 months ago
- Random instruction generator for RISC-V processor verification☆1,224Updated 2 months ago
- Support for Rocket Chip on Zynq FPGAs☆413Updated 6 years ago
- An Agile RISC-V SoC Design Framework with in-order cores, out-of-order cores, accelerators, and more☆2,069Updated 2 weeks ago
- SonicBOOM: The Berkeley Out-of-Order Machine☆2,035Updated 2 weeks ago
- VeeR EH1 core☆914Updated 2 years ago
- RISC-V Formal Verification Framework☆620Updated 3 years ago
- RIDECORE (RIsc-v Dynamic Execution CORE) is an Out-of-Order RISC-V processor written in Verilog HDL.☆369Updated 8 years ago
- 32-bit Superscalar RISC-V CPU☆1,147Updated 4 years ago
- RISC-V Cores, SoC platforms and SoCs☆906Updated 4 years ago
- Chisel examples and code snippets☆263Updated 3 years ago
- OpenXuantie - OpenC910 Core☆1,359Updated last year
- ☆359Updated 3 months ago
- ☆1,092Updated 2 weeks ago
- AXI SystemVerilog synthesizable IP modules and verification infrastructure for high-performance on-chip communication☆1,437Updated last week
- Ibex is a small 32 bit RISC-V CPU core, previously known as zero-riscy.☆1,704Updated 2 weeks ago
- The OpenPiton Platform☆746Updated 2 months ago
- Xilinx Vivado block designs for FPGA RISC-V SoC running Debian Linux distro☆1,028Updated 2 weeks ago
- Common SystemVerilog components☆686Updated this week
- RISC-V Tools (ISA Simulator and Tests)☆1,171Updated 2 years ago
- SCR1 is a high-quality open-source RISC-V MCU core in Verilog☆947Updated last year
- FireSim: Fast and Effortless FPGA-accelerated Hardware Simulation with On-Prem and Cloud Flexibility☆982Updated 6 months ago
- synthesiseable ieee 754 floating point library in verilog☆701Updated 2 years ago
- Parametric floating-point unit with support for standard RISC-V formats and operations as well as transprecision formats.☆548Updated 2 months ago