Alternatives and similar repositories for chisel-tutorial

Users that are interested in chisel-tutorial are comparing it to the libraries listed below

• freechipsproject / chisel-bootcamp
  Generator Bootcamp Material: Learn Chisel the Right Way
  ☆1,066Updated last year
• schoeberl / chisel-book
  Digital Design with Chisel
  ☆858Updated this week
• ucb-bar / riscv-sodor
  educational microarchitectures for risc-v isa
  ☆719Updated last week
• chipsalliance / chisel-template
  A template project for beginning new Chisel work
  ☆661Updated 3 months ago
• ucb-bar / riscv-mini
  Simple RISC-V 3-stage Pipeline in Chisel
  ☆588Updated last year
• chipsalliance / firrtl
  Flexible Intermediate Representation for RTL
  ☆747Updated last year
• openhwgroup / cv32e40p
  CV32E40P is an in-order 4-stage RISC-V RV32IMFCXpulp CPU based on RI5CY from PULP-Platform
  ☆1,112Updated 3 months ago
• ucb-bar / chipyard
  An Agile RISC-V SoC Design Framework with in-order cores, out-of-order cores, accelerators, and more
  ☆1,959Updated this week
• ucb-bar / fpga-zynq
  Support for Rocket Chip on Zynq FPGAs
  ☆412Updated 6 years ago
• riscv-boom / riscv-boom
  SonicBOOM: The Berkeley Out-of-Order Machine
  ☆1,963Updated 4 months ago
• riscvarchive / riscv-cores-list
  RISC-V Cores, SoC platforms and SoCs
  ☆896Updated 4 years ago
• ridecore / ridecore
  RIDECORE (RIsc-v Dynamic Execution CORE) is an Out-of-Order RISC-V processor written in Verilog HDL.
  ☆361Updated 8 years ago
• SymbioticEDA / riscv-formal
  RISC-V Formal Verification Framework
  ☆609Updated 3 years ago
• chipsalliance / riscv-dv
  Random instruction generator for RISC-V processor verification
  ☆1,159Updated 3 months ago
• dawsonjon / fpu
  synthesiseable ieee 754 floating point library in verilog
  ☆671Updated 2 years ago
• schoeberl / chisel-examples
  Chisel examples and code snippets
  ☆258Updated 3 years ago
• chipsalliance / Cores-VeeR-EH1
  VeeR EH1 core
  ☆894Updated 2 years ago
• SpinalHDL / SpinalHDL
  Scala based HDL
  ☆1,847Updated this week
• PrincetonUniversity / openpiton
  The OpenPiton Platform
  ☆729Updated 2 weeks ago
• pulp-platform / axi
  AXI SystemVerilog synthesizable IP modules and verification infrastructure for high-performance on-chip communication
  ☆1,365Updated last week
• pulp-platform / pulp
  This is the top-level project for the PULP Platform. It instantiates a PULP open-source system with a PULP SoC (microcontroller) domain a…
  ☆511Updated 9 months ago
• pulp-platform / common_cells
  Common SystemVerilog components
  ☆654Updated last week
• firesim / firesim
  FireSim: Fast and Effortless FPGA-accelerated Hardware Simulation with On-Prem and Cloud Flexibility
  ☆960Updated 2 months ago
• pulp-platform / ara
  The PULP Ara is a 64-bit Vector Unit, compatible with the RISC-V Vector Extension Version 1.0, working as a coprocessor to CORE-V's CVA6 …
  ☆456Updated last month
• ultraembedded / biriscv
  32-bit Superscalar RISC-V CPU
  ☆1,091Updated 3 years ago
• pulp-platform / pulpissimo
  This is the top-level project for the PULPissimo Platform. It instantiates a PULPissimo open-source system with a PULP SoC domain, but no…
  ☆440Updated 3 months ago
• eugene-tarassov / vivado-risc-v
  Xilinx Vivado block designs for FPGA RISC-V SoC running Debian Linux distro
  ☆992Updated 3 weeks ago
• ucb-bar / chiseltest
  The batteries-included testing and formal verification library for Chisel-based RTL designs.
  ☆233Updated last year
• ucb-bar / berkeley-hardfloat
  ☆341Updated last year
• XUANTIE-RV / openc910
  OpenXuantie - OpenC910 Core
  ☆1,311Updated last year