Alternatives and similar repositories for chisel-tutorial

Users that are interested in chisel-tutorial are comparing it to the libraries listed below

• freechipsproject / chisel-bootcamp
  Generator Bootcamp Material: Learn Chisel the Right Way
  ☆1,042Updated 9 months ago
• schoeberl / chisel-book
  Digital Design with Chisel
  ☆842Updated last month
• chipsalliance / chisel-template
  A template project for beginning new Chisel work
  ☆645Updated last month
• ucb-bar / riscv-sodor
  educational microarchitectures for risc-v isa
  ☆715Updated 3 months ago
• chipsalliance / firrtl
  Flexible Intermediate Representation for RTL
  ☆745Updated 10 months ago
• ucb-bar / riscv-mini
  Simple RISC-V 3-stage Pipeline in Chisel
  ☆581Updated 10 months ago
• openhwgroup / cv32e40p
  CV32E40P is an in-order 4-stage RISC-V RV32IMFCXpulp CPU based on RI5CY from PULP-Platform
  ☆1,080Updated 3 weeks ago
• chipsalliance / riscv-dv
  Random instruction generator for RISC-V processor verification
  ☆1,135Updated 2 weeks ago
• chipsalliance / Cores-VeeR-EH1
  VeeR EH1 core
  ☆883Updated 2 years ago
• SymbioticEDA / riscv-formal
  RISC-V Formal Verification Framework
  ☆602Updated 3 years ago
• lowRISC / ibex
  Ibex is a small 32 bit RISC-V CPU core, previously known as zero-riscy.
  ☆1,568Updated last week
• ucb-bar / chipyard
  An Agile RISC-V SoC Design Framework with in-order cores, out-of-order cores, accelerators, and more
  ☆1,872Updated this week
• ultraembedded / biriscv
  32-bit Superscalar RISC-V CPU
  ☆1,036Updated 3 years ago
• schoeberl / chisel-examples
  Chisel examples and code snippets
  ☆254Updated 2 years ago
• riscv-boom / riscv-boom
  SonicBOOM: The Berkeley Out-of-Order Machine
  ☆1,923Updated last month
• ucb-bar / fpga-zynq
  Support for Rocket Chip on Zynq FPGAs
  ☆409Updated 6 years ago
• pulp-platform / axi
  AXI SystemVerilog synthesizable IP modules and verification infrastructure for high-performance on-chip communication
  ☆1,308Updated this week
• ridecore / ridecore
  RIDECORE (RIsc-v Dynamic Execution CORE) is an Out-of-Order RISC-V processor written in Verilog HDL.
  ☆361Updated 7 years ago
• riscvarchive / riscv-cores-list
  RISC-V Cores, SoC platforms and SoCs
  ☆885Updated 4 years ago
• pulp-platform / pulpissimo
  This is the top-level project for the PULPissimo Platform. It instantiates a PULPissimo open-source system with a PULP SoC domain, but no…
  ☆426Updated last month
• pulp-platform / common_cells
  Common SystemVerilog components
  ☆627Updated this week
• openrisc / mor1kx
  mor1kx - an OpenRISC 1000 processor IP core
  ☆545Updated 2 months ago
• ucb-bar / berkeley-hardfloat
  ☆328Updated 9 months ago
• SpinalHDL / SpinalHDL
  Scala based HDL
  ☆1,799Updated this week
• syntacore / scr1
  SCR1 is a high-quality open-source RISC-V MCU core in Verilog
  ☆918Updated 7 months ago
• openhwgroup / cvfpu
  Parametric floating-point unit with support for standard RISC-V formats and operations as well as transprecision formats.
  ☆501Updated 4 months ago
• openhwgroup / core-v-verif
  Functional verification project for the CORE-V family of RISC-V cores.
  ☆556Updated 2 weeks ago
• PrincetonUniversity / openpiton
  The OpenPiton Platform
  ☆710Updated last month
• dawsonjon / fpu
  synthesiseable ieee 754 floating point library in verilog
  ☆643Updated 2 years ago
• pulp-platform / ara
  The PULP Ara is a 64-bit Vector Unit, compatible with the RISC-V Vector Extension Version 1.0, working as a coprocessor to CORE-V's CVA6 …
  ☆435Updated this week