Alternatives and similar repositories for NutShell-doc:

Users that are interested in NutShell-doc are comparing it to the libraries listed below

• OpenXiangShan / difftest
  Modern co-simulation framework for RISC-V CPUs
  ☆139Updated last week
• DawnCarol / DawnCarol
  ☆186Updated this week
• arch-simulator-sig / advanced-computer-architecture
  体系结构研讨 + ysyx高阶大纲 (WIP
  ☆150Updated 6 months ago
• MaxXSoft / Fuxi
  Fuxi (伏羲) is a 32-bit pipelined RISC-V processor written in Chisel3.
  ☆173Updated 3 years ago
• OSCPU-Zhoushan / Zhoushan
  Open Source Chip Project by University (OSCPU) - Zhoushan Core
  ☆50Updated 2 years ago
• sycuricon / starship
  Run rocket-chip on FPGA
  ☆67Updated 5 months ago
• OpenXiangShan / XiangShan-doc
  Documentation for XiangShan
  ☆410Updated last week
• OSCPU / ysyx
  一生一芯的信息发布和内容网站
  ☆130Updated last year
• shawn110285 / Cookabarra
  a training-target implementation of rv32im, designed to be simple and easy to understand
  ☆58Updated 3 years ago
• microdynamics-cpu / tree-core-ide
  The next generation integrated development environment for processor design and verification. It has multi-hardware language support, o…
  ☆103Updated 2 years ago
• OpenXiangShan / NEMU
  ☆271Updated this week
• OSCPU / ysyxSoC
  ☆85Updated 2 months ago
• cnrv / rocket-chip-read
  Comment on the rocket-chip source code
  ☆178Updated 6 years ago
• whik / e200_opensource
  The Ultra-Low Power RISC Core
  ☆47Updated 5 years ago
• cnrv / fpga-rocket-chip
  Wrapper for Rocket-Chip on FPGAs
  ☆132Updated 2 years ago
• LiHao217 / RISC-V_article_paper_src
  riscv资料、论文等
  ☆143Updated 6 years ago
• cnrv / home
  为推广RISC-V尽些薄力
  ☆312Updated last year
• OpenXiangShan / GEM5
  ☆77Updated this week
• OSCPU / ysyx-workbench
  ☆144Updated 7 months ago
• meton-robean / ResearchNote
  通过issue和README来记录日常学习研究笔记 关注 机器学习系统，深度学习， LLVM，性能剖视， Linux操作系统内核 话题 关注 C/C++. JAVA. Python. Golang. Chisel. 编程语言话题 ( Writing Blogs using …
  ☆75Updated 4 years ago
• ysyx-ta / ysyx-summer-readings
  ☆65Updated 8 months ago
• OpenXiangShan / xs-env
  XiangShan Frontend Develop Environment
  ☆55Updated 2 weeks ago
• ucb-bar / riscv-mini
  Simple RISC-V 3-stage Pipeline in Chisel
  ☆569Updated 8 months ago
• risclite / SuperScalar-RISCV-CPU
  SSRV(Super-Scalar RISC-V) --- Super-scalar out-of-order RV32IMC CPU core, 6.4 CoreMark/MHz.
  ☆210Updated 4 years ago
• riscv-mcu / hbird-sdk
  OpenSource HummingBird RISC-V Software Development Kit
  ☆154Updated last year
• RV-BOSC / OpenNoC
  ☆136Updated last week
• lizhirui / DreamCore
  ☆64Updated 2 years ago
• gzzyyxh / Quafu
  A small SoC with a pipeline 32-bit RISC-V CPU.
  ☆63Updated 2 years ago
• SI-RISCV / hbird-e-sdk
  Deprecated, please go to https://github.com/riscv-mcu/hbird-sdk/
  ☆111Updated 4 years ago
• THU-DSP-LAB / ventus-gpgpu
  GPGPU processor supporting RISCV-V extension, developed with Chisel HDL
  ☆722Updated this week