OSCPU / ysyx
一生一芯的信息发布和内容网站
☆131Updated last year
Alternatives and similar repositories for ysyx:
Users that are interested in ysyx are comparing it to the libraries listed below
- ☆148Updated 2 weeks ago
- ☆66Updated 9 months ago
- ☆63Updated 2 weeks ago
- 体系结构研讨 + ysyx高阶大纲 (WIP☆155Updated 6 months ago
- UltraMIPS SoC composed of dual-issue cpu, pipeline Cache and systematic peripheral.☆132Updated 10 months ago
- ☆86Updated this week
- NJU Virtual Board☆274Updated 2 weeks ago
- Fuxi (伏羲) is a 32-bit pipelined RISC-V processor written in Chisel3.☆172Updated 3 years ago
- 为了更好地帮助后来的同学参加龙芯杯,草拟了这份建议,望对后来人有所帮助☆126Updated 4 years ago
- 复旦大学FDU1.1队在第四届“龙芯杯”的参赛作品☆43Updated 4 years ago
- ☆36Updated last year
- ☆64Updated 2 years ago
- NSCSCC 信息整合☆240Updated 4 years ago
- High performance LA32R out-of-order processor core. (NSCSCC 2023 Special Prize)☆78Updated last year
- Open Source Chip Project by University (OSCPU) - Zhoushan Core☆50Updated 2 years ago
- verilog module add prefix script 可用于ysyx项目添加学号☆13Updated last year
- a Quad-issue, Out-of-order Superscalar MIPS Processor Implemented in SystemVerilog☆47Updated last year
- ☆35Updated last year
- 一生一芯 , ysyx , npc . the repo of the YSYX project . a riscv-64 CPU . writing .☆28Updated 2 years ago
- Naïve MIPS32 SoC implementation☆114Updated 4 years ago
- ☆122Updated 2 years ago
- A small SoC with a pipeline 32-bit RISC-V CPU.☆63Updated 2 years ago
- A tool to decode RISC-V and LoongArch and MIPS instructions in gtkwave☆31Updated 3 weeks ago
- "aura" my super-scalar O3 cpu core☆24Updated 11 months ago
- ☆34Updated 5 years ago
- ☆64Updated 3 months ago
- 龙芯杯个人赛工具包(适用于个人赛的golden_trace工具)☆52Updated last year
- Modern co-simulation framework for RISC-V CPUs☆142Updated this week
- Asymmetric dual issue in-order microprocessor.☆34Updated 5 years ago
- 一生一芯CPU/目前做到cache/后续主要考虑ASIC DV☆19Updated 3 months ago