OSCPU / ysyx
一生一芯的 信息发布和内容网站
☆123Updated last year
Related projects ⓘ
Alternatives and complementary repositories for ysyx
- 体系结构研讨 + ysyx高阶大纲 (WIP☆115Updated last month
- ☆60Updated 3 months ago
- ☆119Updated 2 months ago
- UltraMIPS SoC composed of dual-issue cpu, pipeline Cache and systematic peripheral.☆121Updated 4 months ago
- NJU Virtual Board☆235Updated 3 months ago
- ☆76Updated 2 months ago
- NSCSCC 信息整合☆220Updated 3 years ago
- A tool to decode RISC-V and LoongArch and MIPS instructions in gtkwave☆25Updated 7 months ago
- 为了更好地帮助后来的同学参加龙芯杯，草拟了这份建议，望对后来人有所帮助☆113Updated 4 years ago
- ☆116Updated 2 years ago
- ☆56Updated 4 months ago
- 龙芯杯个人赛工具包（适用于个人赛的golden_trace工具）☆48Updated 8 months ago
- Fuxi (伏羲) is a 32-bit pipelined RISC-V processor written in Chisel3.☆162Updated 3 years ago
- ☆43Updated 4 months ago
- Modern co-simulation framework for RISC-V CPUs☆117Updated this week
- verilog module add prefix script 可用于ysyx项目添加学号☆13Updated 8 months ago
- 复旦大学FDU1.1队在第四届“龙芯杯”的参赛作品☆40Updated 4 years ago
- 一生一芯 ， ysyx ， npc . the repo of the YSYX project . a riscv-64 CPU . writing .☆24Updated 2 years ago
- ☆52Updated last year
- ☆20Updated 11 months ago
- How to make undergraduates or new graduates ready for advanced computer architecture research or modern CPU design☆476Updated 3 months ago
- A small SoC with a pipeline 32-bit RISC-V CPU.☆62Updated 2 years ago
- 2022年龙芯杯个人赛 单发射110M（含icache）☆44Updated 2 years ago
- Naïve MIPS32 SoC implementation☆113Updated 4 years ago
- ☆33Updated 5 years ago
- Open Source Chip Project by University (OSCPU) - Zhoushan Core☆46Updated 2 years ago
- ☆32Updated last year
- Documentation for XiangShan☆351Updated last week
- An exquisite superscalar RV32GC processor.☆143Updated 6 months ago