MPSLab-ASU / ccfLinks
CGRA Compilation Framework
☆83Updated last year
Alternatives and similar repositories for ccf
Users that are interested in ccf are comparing it to the libraries listed below
Sorting:
- An MLIR dialect to enable the efficient acceleration of ML model on CGRAs.☆59Updated 7 months ago
- Benchmarks for Accelerator Design and Customized Architectures☆122Updated 5 years ago
- An integrated CGRA design framework☆88Updated 2 months ago
- ☆91Updated last year
- ☆86Updated last year
- EQueue Dialect☆40Updated 3 years ago
- An Open-Source Tool for CGRA Accelerators☆65Updated last month
- ☆58Updated last year
- CGRA-Flow is an integrated framework for CGRA compilation, exploration, synthesis, and development.☆129Updated last week
- Tests for example Rocket Custom Coprocessors☆74Updated 5 years ago
- Implementations of Buffets, which are efficient, composable idioms for implementing Explicit Decoupled Data Orchestration.☆71Updated 6 years ago
- Release of stream-specialization software/hardware stack.☆121Updated 2 years ago
- Template-based Reconfigurable Architecture Modeling Framework☆14Updated 2 years ago
- An LLVM pass that can generate CDFG and map the target loops onto a parameterizable CGRA.☆72Updated 3 weeks ago
- Simulator framework for analysis of performance, energy consumption, area and cost of multi-node multi-chiplet tile-based manycore design…☆67Updated 11 months ago
- ☆59Updated this week
- OpenCGRA is an open-source framework for modeling, testing, and evaluating CGRAs.☆152Updated 2 years ago
- CGRA framework with vectorization support.☆30Updated 3 weeks ago
- ☆44Updated this week
- Fork of seldridge/rocket-rocc-examples with tests for a systolic array based matmul accelerator☆59Updated 3 months ago
- Dynamically Reconfigurable Architecture Template and Cycle-level Microarchitecture Simulator for Dataflow AcCelerators☆28Updated last year
- dMazeRunner: Dataflow acceleration optimization infrastructure for coarse-grained programmable accelerators☆45Updated 3 years ago
- ☆15Updated 2 years ago
- An example of using Ramulator as memory model in a cycle-accurate SystemC Design☆50Updated 7 years ago
- An open-source DRAM power model based on extensive experimental characterization of real DRAM modules. Described in the SIGMETRICS 2018 …☆39Updated 6 years ago
- The programming runtime and interfaces for ARENA.☆14Updated 3 years ago
- ILA Model Database☆22Updated 4 years ago
- ☆15Updated 2 years ago
- A 32-bit RISC-V Processor Designed with High-Level Synthesis☆52Updated 5 years ago
- A hardware synthesis framework with multi-level paradigm☆39Updated 4 months ago