Kuree / cgra_pnrLinks
Fast PnR toolchain for CGRA
☆18Updated last year
Alternatives and similar repositories for cgra_pnr
Users that are interested in cgra_pnr are comparing it to the libraries listed below
Sorting:
- The PE for the second generation CGRA (garnet).☆17Updated 5 months ago
- ☆103Updated 3 years ago
- ESI is an FPGA connectivity system. It uses typed, latency-insensitive on-chip connections between ESI-enabled modules. It also bridges o…☆34Updated 5 years ago
- Lake is a framework for generating synthesizable memory modules from a high-level behavioral specification and widely-available memory ma…☆22Updated this week
- Debuggable hardware generator☆70Updated 2 years ago
- A fault-injection framework using Chisel and FIRRTL☆37Updated 2 weeks ago
- Hardware generator debugger☆76Updated last year
- design and verification of asynchronous circuits☆40Updated this week
- Using e-graphs to synthesize netlists from boolean logic.☆14Updated 2 years ago
- ☆56Updated 3 years ago
- Fluid Pipelines☆11Updated 7 years ago
- ILA Model Database☆23Updated 5 years ago
- LLVM based HLS library for HWToolkit (hardware devel. toolkit)☆25Updated 2 months ago
- OpenDesign Flow Database☆16Updated 6 years ago
- Matchlib Connections Library - latency insensitive channels (from NVlabs/matchlib/connections)☆43Updated 2 weeks ago
- The ANUBIS benchmark suite for Incremental Synthesis☆12Updated 4 years ago
- Benchmarks for Yosys development☆24Updated 5 years ago
- ☆15Updated 5 years ago
- Next generation CGRA generator☆114Updated this week
- A tool that converts SystemVerilog to Verilog. Uses Design Compiler, so it is 100% compatible.☆42Updated 2 years ago
- GL0AM GPU Accelerated Gate Level Logic Simulator☆27Updated last month
- ☆23Updated 4 years ago
- A configurable SRAM generator☆54Updated last month
- ☆31Updated 2 years ago
- A SystemVerilog language server based on the Slang parser and library.☆36Updated last week
- Collection of test cases for Yosys☆18Updated 3 years ago
- Verilog Fuzzer to test the major simulators and sythesisers by generating random, valid Verilog.☆115Updated 4 months ago
- A GPU acceleration flow for RTL simulation with batch stimulus☆113Updated last year
- DASS HLS Compiler☆29Updated 2 years ago
- Equivalence checking with Yosys☆46Updated last week