Alternatives and similar repositories for cgra_pnr

Users that are interested in cgra_pnr are comparing it to the libraries listed below

• broccolimicro / loom
  design and verification of asynchronous circuits
  ☆41Updated 3 weeks ago
• rdaly525 / coreir
  ☆104Updated 3 years ago
• StanfordAHA / lassen
  The PE for the second generation CGRA (garnet).
  ☆17Updated 6 months ago
• Kuree / kratos
  Debuggable hardware generator
  ☆70Updated 2 years ago
• StanfordAHA / lake
  Lake is a framework for generating synthesizable memory modules from a high-level behavioral specification and widely-available memory ma…
  ☆22Updated this week
• Kuree / hgdb
  Hardware generator debugger
  ☆76Updated last year
• microsoft / Elastic-Silicon-Interconnect
  ESI is an FPGA connectivity system. It uses typed, latency-insensitive on-chip connections between ESI-enabled modules. It also bridges o…
  ☆34Updated 5 years ago
• rahulk29 / sram22
  A configurable SRAM generator
  ☆56Updated 2 months ago
• chipsalliance / fpga-interchange-schema
  ☆56Updated 3 years ago
• ymherklotz / verismith
  Verilog Fuzzer to test the major simulators and sythesisers by generating random, valid Verilog.
  ☆116Updated 5 months ago
• jinwookjungs / open_design_flow
  OpenDesign Flow Database
  ☆16Updated 6 years ago
• mikeurbach / egg-netlist-synthesizer
  Using e-graphs to synthesize netlists from boolean logic.
  ☆14Updated 2 years ago
• IBM / chiffre
  A fault-injection framework using Chisel and FIRRTL
  ☆36Updated last month
• ucb-substrate / substrate2
  21st century electronic design automation tools, written in Rust.
  ☆31Updated last week
• YosysHQ / yosys-bench
  Benchmarks for Yosys development
  ☆24Updated 5 years ago
• masc-ucsc / fluid
  Fluid Pipelines
  ☆11Updated 7 years ago
• bespoke-silicon-group / bsg_fakeram
  fakeram generator for use by researchers who do not have access to commercial ram generators
  ☆37Updated 2 years ago
• AUCOHL / Lighter
  An automatic clock gating utility
  ☆50Updated 6 months ago
• The-OpenROAD-Project-Attic / Resizer
  ☆15Updated 6 years ago
• PrincetonUniversity / IMDb-Archive
  ILA Model Database
  ☆24Updated 5 years ago
• leonardt / fault
  A Python package for testing hardware (part of the magma ecosystem)
  ☆45Updated last year
• pulp-platform / ELAU
  ☆19Updated last year
• YosysHQ / yosys-tests
  Collection of test cases for Yosys
  ☆17Updated 3 years ago
• bespoke-silicon-group / bsg_sv2v
  A tool that converts SystemVerilog to Verilog. Uses Design Compiler, so it is 100% compatible.
  ☆43Updated 2 years ago
• scale-lab / BLASYS
  An Approximate Logic Synthesis Framework based on Boolean Matrix Factorization
  ☆31Updated last year
• StanfordAHA / garnet
  Next generation CGRA generator
  ☆115Updated this week
• masc-ucsc / anubis
  The ANUBIS benchmark suite for Incremental Synthesis
  ☆12Updated 4 years ago
• jameshanlon / netlist-paths
  A library and command-line tool for querying a Verilog netlist.
  ☆28Updated 3 years ago
• hplp / aes_chisel
  Implementation of the Advanced Encryption Standard in Chisel
  ☆19Updated 3 years ago
• ckchengucsd / SMT-based-STDCELL-Layout-Generator-for-PROBE2.0
  SMT-based Simultaneous Place-&-Route for Standard Cell Synthesis for PROBE 2.0
  ☆18Updated 5 years ago