Kuree / cgra_pnr
Fast PnR toolchain for CGRA
☆18Updated 8 months ago
Alternatives and similar repositories for cgra_pnr:
Users that are interested in cgra_pnr are comparing it to the libraries listed below
- The PE for the second generation CGRA (garnet).☆17Updated 2 weeks ago
- DASS HLS Compiler☆29Updated last year
- Lake is a framework for generating synthesizable memory modules from a high-level behavioral specification and widely-available memory ma…☆21Updated this week
- Using e-graphs to synthesize netlists from boolean logic.☆14Updated last year
- Fluid Pipelines☆11Updated 6 years ago
- ESI is an FPGA connectivity system. It uses typed, latency-insensitive on-chip connections between ESI-enabled modules. It also bridges o…☆34Updated 4 years ago
- OpenDesign Flow Database☆16Updated 6 years ago
- An Approximate Logic Synthesis Framework based on Boolean Matrix Factorization☆30Updated last year
- Open source RTL simulation acceleration on commodity hardware☆25Updated 2 years ago
- An automatic clock gating utility☆46Updated this week
- ☆55Updated 2 years ago
- The ANUBIS benchmark suite for Incremental Synthesis☆12Updated 4 years ago
- ☆23Updated 4 years ago
- Benchmarks for Yosys development☆24Updated 5 years ago
- Implementation of the Advanced Encryption Standard in Chisel☆20Updated 3 years ago
- ☆31Updated last year
- Documentation for the entire CGRAFlow☆19Updated 3 years ago
- A configurable SRAM generator☆47Updated 3 months ago
- Papers, Posters, Presentations, Documentation...☆18Updated last year
- ☆15Updated 2 years ago
- SimCommand is a library for writing high-performance RTL testbenches with simulation threads in Scala using chiseltest.☆14Updated last year
- Hardware generator debugger☆73Updated last year
- ☆31Updated 3 months ago
- Integration test for entire CGRA flow☆12Updated 5 years ago
- Runtime-First FPGA Interchange Routing Contest @ FPGA’24☆33Updated last month
- Cross EDA Abstraction and Automation☆36Updated this week
- A Vivado HLS Command Line Helper Tool☆36Updated 3 years ago
- ☆14Updated 5 years ago
- An open source generator for standard cell based memories.☆13Updated 8 years ago
- 🕒 Static Timing Analysis diagram renderer☆13Updated last year