Alternatives and similar repositories for cgra_pnr

Users that are interested in cgra_pnr are comparing it to the libraries listed below

• chipsalliance / fpga-interchange-schema
  ☆59Updated 3 years ago
• broccolimicro / loom
  design and verification of asynchronous circuits
  ☆42Updated 3 weeks ago
• NVlabs / GL0AM
  GL0AM GPU Accelerated Gate Level Logic Simulator
  ☆29Updated 4 months ago
• Kuree / kratos
  Debuggable hardware generator
  ☆70Updated 2 years ago
• Kuree / hgdb
  Hardware generator debugger
  ☆77Updated last year
• rdaly525 / coreir
  ☆104Updated 3 years ago
• AUCOHL / Lighter
  An automatic clock gating utility
  ☆51Updated 8 months ago
• rahulk29 / sram22
  A configurable SRAM generator
  ☆56Updated 4 months ago
• scale-lab / BLASYS
  An Approximate Logic Synthesis Framework based on Boolean Matrix Factorization
  ☆32Updated 2 years ago
• mikeurbach / egg-netlist-synthesizer
  Using e-graphs to synthesize netlists from boolean logic.
  ☆14Updated 2 years ago
• StanfordAHA / lassen
  The PE for the second generation CGRA (garnet).
  ☆17Updated 8 months ago
• microsoft / Elastic-Silicon-Interconnect
  ESI is an FPGA connectivity system. It uses typed, latency-insensitive on-chip connections between ESI-enabled modules. It also bridges o…
  ☆35Updated 5 years ago
• jinwookjungs / open_design_flow
  OpenDesign Flow Database
  ☆17Updated 7 years ago
• dian-lun-lin / RTLflow
  A GPU acceleration flow for RTL simulation with batch stimulus
  ☆116Updated last year
• StanfordAHA / lake
  Lake is a framework for generating synthesizable memory modules from a high-level behavioral specification and widely-available memory ma…
  ☆23Updated this week
• YosysHQ / yosys-bench
  Benchmarks for Yosys development
  ☆24Updated 5 years ago
• ABKGroup / RosettaStone
  ☆32Updated 3 years ago
• StanfordAHA / garnet
  Next generation CGRA generator
  ☆118Updated this week
• dillonhuff / ahaHLS
  An open source high level synthesis (HLS) tool built on top of LLVM
  ☆127Updated last year
• vegaluisjose / vast
  Verilog AST
  ☆21Updated 2 years ago
• ymherklotz / verismith
  Verilog Fuzzer to test the major simulators and sythesisers by generating random, valid Verilog.
  ☆116Updated 7 months ago
• ucb-substrate / substrate2
  21st century electronic design automation tools, written in Rust.
  ☆33Updated this week
• Intuity / nexus
  Open source RTL simulation acceleration on commodity hardware
  ☆33Updated 2 years ago
• pulp-platform / ELAU
  ☆20Updated last year
• Xilinx / fpga24_routing_contest
  Runtime-First FPGA Interchange Routing Contest @ FPGA’24
  ☆34Updated 7 months ago
• hplp / aes_chisel
  Implementation of the Advanced Encryption Standard in Chisel
  ☆19Updated 3 years ago
• circt-hls / circt-hls
  CIRCT-based HLS compilation flows, debugging, and cosimulation tools.
  ☆53Updated 2 years ago
• woset-workshop / woset-workshop.github.io
  Workshop on Open-Source EDA Technology (WOSET)
  ☆48Updated last year
• leonardt / hwtypes
  Python implementations of fixed size hardware types (Bit, BitVector, UInt, SInt, ...) based on the SMT-LIB2 semantics
  ☆18Updated 2 years ago
• The-OpenROAD-Project / alpha-release
  Builds, flow and designs for the alpha release
  ☆54Updated 6 years ago