tancheng / CGRA-FlowLinks
CGRA-Flow is an integrated framework for CGRA compilation, exploration, synthesis, and development.
☆143Updated last week
Alternatives and similar repositories for CGRA-Flow
Users that are interested in CGRA-Flow are comparing it to the libraries listed below
Sorting:
- OpenCGRA is an open-source framework for modeling, testing, and evaluating CGRAs.☆161Updated 2 years ago
- An integrated CGRA design framework☆91Updated 7 months ago
- An LLVM pass that can generate CDFG and map the target loops onto a parameterizable CGRA.☆78Updated last month
- TAPA compiles task-parallel HLS program into high-performance FPGA accelerators.☆175Updated 3 months ago
- An Open-Source Tool for CGRA Accelerators☆76Updated 2 months ago
- An MLIR dialect to enable the efficient acceleration of ML model on CGRAs.☆64Updated last year
- AutoSA: Polyhedral-Based Systolic Array Compiler☆229Updated 2 years ago
- CGRA framework with vectorization support.☆39Updated this week
- [FPGA 2021, Best Paper Award] An automated floorplanning and pipelining tool for Vivado HLS.☆127Updated 2 years ago
- CGRA Compilation Framework☆88Updated 2 years ago
- ☆87Updated last year
- Rosetta: A Realistic High-level Synthesis Benchmark Suite for Software Programmable FPGAs (FPGA'18)☆168Updated 2 years ago
- ☆60Updated 7 months ago
- ☆53Updated 4 months ago
- ☆61Updated this week
- Benchmarks for Accelerator Design and Customized Architectures☆135Updated 5 years ago
- A Chisel RTL generator for network-on-chip interconnects☆221Updated last week
- An Open-Source Tool for CGRA Accelerators☆25Updated 2 months ago
- ☆15Updated 3 weeks ago
- An MLIR Complier for PyTorch/C/C++ Codes into HLS Dataflow Designs☆51Updated 3 months ago
- gem5 repository to study chiplet-based systems☆84Updated 6 years ago
- An Open-Hardware CGRA for accelerated computation on the edge.☆38Updated 2 weeks ago
- High-Performance Sparse Linear Algebra on HBM-Equipped FPGAs Using HLS☆95Updated last year
- ☆44Updated last year
- A toolchain for rapid design space exploration of chiplet architectures☆66Updated 3 months ago
- ☆105Updated last year
- Implementations of Buffets, which are efficient, composable idioms for implementing Explicit Decoupled Data Orchestration.☆79Updated 6 years ago
- A DSL for Systolic Arrays☆82Updated 6 years ago
- Deep Learning Accelerator Based on Eyeriss V2 Architecture with custom RISC-V extended instructions☆204Updated 5 years ago
- Release of stream-specialization software/hardware stack.☆119Updated 2 years ago