tancheng / CGRA-FlowLinks
CGRA-Flow is an integrated framework for CGRA compilation, exploration, synthesis, and development.
☆138Updated 4 months ago
Alternatives and similar repositories for CGRA-Flow
Users that are interested in CGRA-Flow are comparing it to the libraries listed below
Sorting:
- OpenCGRA is an open-source framework for modeling, testing, and evaluating CGRAs.☆160Updated 2 years ago
- An integrated CGRA design framework☆91Updated 7 months ago
- An Open-Source Tool for CGRA Accelerators☆74Updated last month
- TAPA compiles task-parallel HLS program into high-performance FPGA accelerators.☆175Updated 2 months ago
- An LLVM pass that can generate CDFG and map the target loops onto a parameterizable CGRA.☆74Updated 2 weeks ago
- An MLIR dialect to enable the efficient acceleration of ML model on CGRAs.☆64Updated last year
- AutoSA: Polyhedral-Based Systolic Array Compiler☆224Updated 2 years ago
- An Open-Source Tool for CGRA Accelerators☆25Updated last month
- Rosetta: A Realistic High-level Synthesis Benchmark Suite for Software Programmable FPGAs☆167Updated last year
- [FPGA 2021, Best Paper Award] An automated floorplanning and pipelining tool for Vivado HLS.☆126Updated 2 years ago
- ☆50Updated 3 months ago
- ☆87Updated last year
- CGRA framework with vectorization support.☆35Updated last week
- CGRA Compilation Framework☆88Updated 2 years ago
- Benchmarks for Accelerator Design and Customized Architectures☆130Updated 5 years ago
- A Chisel RTL generator for network-on-chip interconnects☆215Updated 2 months ago
- ☆61Updated this week
- ☆60Updated 7 months ago
- An MLIR Complier for PyTorch/C/C++ Codes into HLS Dataflow Designs☆49Updated 2 months ago
- Implementations of Buffets, which are efficient, composable idioms for implementing Explicit Decoupled Data Orchestration.☆78Updated 6 years ago
- An Open-Hardware CGRA for accelerated computation on the edge.☆35Updated last year
- ☆44Updated last year
- CHARM: Composing Heterogeneous Accelerators on Heterogeneous SoC Architecture☆157Updated this week
- Template-based Reconfigurable Architecture Modeling Framework☆14Updated 3 years ago
- High-Performance Sparse Linear Algebra on HBM-Equipped FPGAs Using HLS☆95Updated last year
- A RISC-V BOOM Microarchitecture Power Modeling Framework☆30Updated 2 years ago
- gem5 repository to study chiplet-based systems☆82Updated 6 years ago
- An FPGA accelerator for general-purpose Sparse-Matrix Dense-Matrix Multiplication (SpMM).☆87Updated last year
- ☆101Updated last year
- A 32-bit RISC-V Processor Designed with High-Level Synthesis☆54Updated 5 years ago