tancheng / CGRA-FlowLinks
CGRA-Flow is an integrated framework for CGRA compilation, exploration, synthesis, and development.
☆138Updated 3 months ago
Alternatives and similar repositories for CGRA-Flow
Users that are interested in CGRA-Flow are comparing it to the libraries listed below
Sorting:
- OpenCGRA is an open-source framework for modeling, testing, and evaluating CGRAs.☆160Updated 2 years ago
- An integrated CGRA design framework☆91Updated 6 months ago
- An Open-Source Tool for CGRA Accelerators☆74Updated 3 weeks ago
- TAPA compiles task-parallel HLS program into high-performance FPGA accelerators.☆174Updated last month
- An LLVM pass that can generate CDFG and map the target loops onto a parameterizable CGRA.☆74Updated last month
- AutoSA: Polyhedral-Based Systolic Array Compiler☆225Updated 2 years ago
- An MLIR dialect to enable the efficient acceleration of ML model on CGRAs.☆63Updated 11 months ago
- [FPGA 2021, Best Paper Award] An automated floorplanning and pipelining tool for Vivado HLS.☆125Updated 2 years ago
- An Open-Source Tool for CGRA Accelerators☆24Updated 3 weeks ago
- ☆49Updated 3 months ago
- Rosetta: A Realistic High-level Synthesis Benchmark Suite for Software Programmable FPGAs☆167Updated last year
- CGRA Compilation Framework☆88Updated 2 years ago
- A Chisel RTL generator for network-on-chip interconnects☆211Updated last month
- ☆59Updated 6 months ago
- ☆61Updated this week
- ☆87Updated last year
- Implementations of Buffets, which are efficient, composable idioms for implementing Explicit Decoupled Data Orchestration.☆77Updated 6 years ago
- Benchmarks for Accelerator Design and Customized Architectures☆129Updated 5 years ago
- An MLIR Complier for PyTorch/C/C++ Codes into HLS Dataflow Designs☆47Updated 2 months ago
- The RAD flow is an open-source academic architecture exploration and evaluation flow for novel beyond-FPGA reconfigurable acceleration de…☆38Updated 2 months ago
- CGRA framework with vectorization support.☆35Updated last week
- An Open-Hardware CGRA for accelerated computation on the edge.☆35Updated last year
- High-Performance Sparse Linear Algebra on HBM-Equipped FPGAs Using HLS☆95Updated last year
- A RISC-V BOOM Microarchitecture Power Modeling Framework☆29Updated 2 years ago
- CHARM: Composing Heterogeneous Accelerators on Heterogeneous SoC Architecture☆157Updated this week
- Template-based Reconfigurable Architecture Modeling Framework☆14Updated 3 years ago
- A systolic array simulator for multi-cycle MACs and varying-byte words, with the paper accepted to HPCA 2022.☆80Updated 3 years ago
- HW Architecture-Mapping Design Space Exploration Framework for Deep Learning Accelerators☆160Updated last month
- A DSL for Systolic Arrays☆81Updated 6 years ago
- ☆63Updated 5 months ago