Blaok / fpga-runtime
☆12Updated 5 months ago
Alternatives and similar repositories for fpga-runtime:
Users that are interested in fpga-runtime are comparing it to the libraries listed below
- HeteroHalide: From Image Processing DSL to Efficient FPGA Acceleration☆15Updated 4 years ago
- TAPA is a dataflow HLS framework that features fast compilation, expressive programming model and generates high-frequency FPGA accelerat…☆19Updated 5 months ago
- Dynamically Reconfigurable Architecture Template and Cycle-level Microarchitecture Simulator for Dataflow AcCelerators☆28Updated last year
- The Next-gen Language & Compiler Powering Efficient Hardware Design☆21Updated 2 weeks ago
- Domain-Specific Architecture Generator 2☆21Updated 2 years ago
- Accelerating SSSP for power-law graphs using an FPGA.☆23Updated 2 years ago
- ☆23Updated 4 years ago
- Polyhedral High-Level Synthesis in MLIR☆30Updated last year
- ☆23Updated 4 years ago
- dMazeRunner: Dataflow acceleration optimization infrastructure for coarse-grained programmable accelerators☆45Updated 2 years ago
- A fast, accurate trace-based simulator for High-Level Synthesis.☆40Updated 8 months ago
- AIM: Accelerating Arbitrary-precision Integer Multiplication on Heterogeneous Reconfigurable Computing Platform Versal ACAP (Full Paper a…☆22Updated 4 months ago
- Stencil with Optimized Dataflow Architecture Compiler☆16Updated 4 years ago
- ☆16Updated 2 years ago
- A synthesis flow for hybrid processing-in-RRAM modes☆12Updated 3 years ago
- ☆33Updated 3 years ago
- CGRA framework with vectorization support.☆21Updated this week
- A graph linear algebra overlay☆50Updated last year
- ICCAD'23 Best Paper Award candidate: Robust GNN-based Representation Learning for HLS☆15Updated 8 months ago
- DASS HLS Compiler☆27Updated last year
- Productive and portable performance programming across spatial architectures (FPGAs, etc.) and vector architectures (GPUs, etc.)☆30Updated 8 months ago
- PARADE: A Cycle-Accurate Full-System Simulation Platform for Accelerator-Rich Architectural Design and Exploration☆46Updated 2 years ago
- [DAC 2020] Analysis and Optimization of the Implicit Broadcasts in FPGA HLS to Improve Maximum Frequency☆32Updated 3 years ago
- STONNE Simulator integrated into SST Simulator☆17Updated 9 months ago
- [FPGA'21] Microbenchmarks for Demystifying the Memory System of Modern Datacenter FPGAs for Software Programmers☆30Updated 3 years ago
- agile hardware-software co-design☆47Updated 3 years ago
- ☆25Updated 3 years ago
- A high-level performance analysis tool for FPGA-based accelerators☆19Updated 7 years ago
- ☆13Updated 2 years ago
- High-Performance Sparse Linear Algebra on HBM-Equipped FPGAs Using HLS☆84Updated 4 months ago