Blaok / fpga-runtime
☆11Updated 3 months ago
Related projects ⓘ
Alternatives and complementary repositories for fpga-runtime
- TAPA is a dataflow HLS framework that features fast compilation, expressive programming model and generates high-frequency FPGA accelerat…☆19Updated 2 months ago
- A graph linear algebra overlay☆49Updated last year
- Graph accelerator on FPGAs and ASICs☆12Updated 6 years ago
- Domain-Specific Architecture Generator 2☆20Updated 2 years ago
- agile hardware-software co-design☆46Updated 2 years ago
- Productive and portable performance programming across spatial architectures (FPGAs, etc.) and vector architectures (GPUs, etc.)☆29Updated 6 months ago
- HeteroHalide: From Image Processing DSL to Efficient FPGA Acceleration☆15Updated 4 years ago
- The programming runtime and interfaces for ARENA.☆14Updated 3 years ago
- Dynamically Reconfigurable Architecture Template and Cycle-level Microarchitecture Simulator for Dataflow AcCelerators☆28Updated last year
- A high-level performance analysis tool for FPGA-based accelerators☆18Updated 7 years ago
- A synthesis flow for hybrid processing-in-RRAM modes☆12Updated 3 years ago
- A Full-System Framework for Simulating NDP devices from Caches to DRAM☆14Updated 10 months ago
- Multi-target compiler for Sum-Product Networks, based on MLIR and LLVM.☆23Updated last week
- Accelerating SSSP for power-law graphs using an FPGA.☆21Updated 2 years ago
- AIM: Accelerating Arbitrary-precision Integer Multiplication on Heterogeneous Reconfigurable Computing Platform Versal ACAP (Full Paper a…☆21Updated last month
- HeteroCL-MLIR dialect for accelerator design☆40Updated 2 months ago
- EQueue Dialect☆39Updated 2 years ago
- A fast, accurate trace-based simulator for High-Level Synthesis.☆38Updated 6 months ago
- ☆23Updated 3 years ago
- Code base for OOPSLA'24 paper: UniSparse: An Intermediate Language for General Sparse Format Customization☆28Updated last week
- Polyhedral High-Level Synthesis in MLIR☆29Updated last year
- ☆25Updated 7 months ago
- CGRA framework with vectorization support.☆19Updated this week
- ☆23Updated 4 years ago
- 📥 🎯 (1,4/4) an MLIR-based toolchain with Vitis HLS LLVM input/output targeting FPGAs.☆13Updated 2 years ago
- ☆33Updated 3 years ago
- Stencil with Optimized Dataflow Architecture Compiler☆16Updated 4 years ago
- A hardware design framework with a timing-deterministic, Rust-embedded HDL and the compilation flow.☆12Updated 8 months ago
- STONNE Simulator integrated into SST Simulator☆17Updated 7 months ago
- Fibertree emulator☆12Updated 3 weeks ago