pnnl / OpenCGRALinks
OpenCGRA is an open-source framework for modeling, testing, and evaluating CGRAs.
☆161Updated 2 years ago
Alternatives and similar repositories for OpenCGRA
Users that are interested in OpenCGRA are comparing it to the libraries listed below
Sorting:
- CGRA-Flow is an integrated framework for CGRA compilation, exploration, synthesis, and development.☆143Updated this week
- An Open-Source Tool for CGRA Accelerators☆76Updated 2 months ago
- An LLVM pass that can generate CDFG and map the target loops onto a parameterizable CGRA.☆78Updated last month
- An integrated CGRA design framework☆91Updated 7 months ago
- AutoSA: Polyhedral-Based Systolic Array Compiler☆229Updated 2 years ago
- TAPA compiles task-parallel HLS program into high-performance FPGA accelerators.☆175Updated 2 months ago
- ☆53Updated 4 months ago
- Benchmarks for Accelerator Design and Customized Architectures☆135Updated 5 years ago
- An MLIR dialect to enable the efficient acceleration of ML model on CGRAs.☆64Updated last year
- ☆87Updated last year
- Simulator framework for analysis of performance, energy consumption, area and cost of multi-node multi-chiplet tile-based manycore design…☆72Updated last year
- CGRA framework with vectorization support.☆39Updated this week
- ☆61Updated this week
- A Chisel RTL generator for network-on-chip interconnects☆218Updated last week
- ☆60Updated 7 months ago
- An Open-Source Tool for CGRA Accelerators☆25Updated 2 months ago
- [FPGA 2021, Best Paper Award] An automated floorplanning and pipelining tool for Vivado HLS.☆127Updated 2 years ago
- Rosetta: A Realistic High-level Synthesis Benchmark Suite for Software Programmable FPGAs (FPGA'18)☆168Updated 2 years ago
- CGRA Compilation Framework☆88Updated 2 years ago
- A scalable High-Level Synthesis framework on MLIR☆282Updated last year
- An Open-Hardware CGRA for accelerated computation on the edge.☆37Updated 2 weeks ago
- An FPGA accelerator for general-purpose Sparse-Matrix Dense-Matrix Multiplication (SpMM).☆91Updated last year
- CHARM: Composing Heterogeneous Accelerators on Heterogeneous SoC Architecture☆159Updated this week
- DRAMSys a SystemC TLM-2.0 based DRAM simulator.☆317Updated last month
- Tests for example Rocket Custom Coprocessors☆75Updated 5 years ago
- PyTorch model to RTL flow for low latency inference☆130Updated last year
- Implementations of Buffets, which are efficient, composable idioms for implementing Explicit Decoupled Data Orchestration.☆79Updated 6 years ago
- End-to-end SoC simulation: integrating the gem5 system simulator with the Aladdin accelerator simulator.☆251Updated 3 years ago
- An integrated power, area, and timing modeling framework for multicore and manycore architectures☆202Updated 5 years ago
- HW Architecture-Mapping Design Space Exploration Framework for Deep Learning Accelerators☆165Updated 3 weeks ago