pnnl / OpenCGRALinks
OpenCGRA is an open-source framework for modeling, testing, and evaluating CGRAs.
☆166Updated 2 years ago
Alternatives and similar repositories for OpenCGRA
Users that are interested in OpenCGRA are comparing it to the libraries listed below
Sorting:
- CGRA-Flow is an integrated framework for CGRA compilation, exploration, synthesis, and development.☆152Updated last week
- An Open-Source Tool for CGRA Accelerators☆81Updated 4 months ago
- An integrated CGRA design framework☆91Updated 10 months ago
- An LLVM pass that can generate CDFG and map the target loops onto a parameterizable CGRA.☆79Updated 3 weeks ago
- ☆87Updated last year
- ☆56Updated 6 months ago
- TAPA compiles task-parallel HLS program into high-performance FPGA accelerators. UCLA-maintained.☆177Updated 5 months ago
- An MLIR dialect to enable the efficient acceleration of ML model on CGRAs.☆64Updated last year
- An Open-Source Tool for CGRA Accelerators☆28Updated 4 months ago
- CGRA framework with vectorization support.☆42Updated this week
- Benchmarks for Accelerator Design and Customized Architectures☆136Updated 5 years ago
- AutoSA: Polyhedral-Based Systolic Array Compiler☆236Updated 3 years ago
- [FPGA 2021, Best Paper Award] An automated floorplanning and pipelining tool for Vivado HLS.☆127Updated 3 years ago
- ☆62Updated 10 months ago
- CGRA Compilation Framework☆91Updated 2 years ago
- ☆62Updated this week
- DRAMSys a SystemC TLM-2.0 based DRAM simulator.☆332Updated last week
- An integrated power, area, and timing modeling framework for multicore and manycore architectures☆210Updated 5 years ago
- An Open-Hardware CGRA for accelerated computation on the edge.☆41Updated 2 months ago
- Simulator framework for analysis of performance, energy consumption, area and cost of multi-node multi-chiplet tile-based manycore design…☆74Updated last year
- End-to-end SoC simulation: integrating the gem5 system simulator with the Aladdin accelerator simulator.☆255Updated 3 years ago
- A scalable High-Level Synthesis framework on MLIR☆287Updated last year
- Implementations of Buffets, which are efficient, composable idioms for implementing Explicit Decoupled Data Orchestration.☆82Updated 6 years ago
- An FPGA accelerator for general-purpose Sparse-Matrix Dense-Matrix Multiplication (SpMM).☆92Updated last year
- A Chisel RTL generator for network-on-chip interconnects☆224Updated 2 months ago
- A DSL for Systolic Arrays☆83Updated 7 years ago
- ☆109Updated last year
- Tests for example Rocket Custom Coprocessors☆75Updated 5 years ago
- The RAD flow is an open-source academic architecture exploration and evaluation flow for novel beyond-FPGA reconfigurable acceleration de…☆38Updated 6 months ago
- CHARM: Composing Heterogeneous Accelerators on Heterogeneous SoC Architecture☆162Updated last week