Alternatives and similar repositories for OpenCGRA

Users that are interested in OpenCGRA are comparing it to the libraries listed below

• tancheng / CGRA-Flow
  CGRA-Flow is an integrated framework for CGRA compilation, exploration, synthesis, and development.
  ☆145Updated 2 weeks ago
• tancheng / CGRA-Mapper
  An LLVM pass that can generate CDFG and map the target loops onto a parameterizable CGRA.
  ☆80Updated last week
• ecolab-nus / morpher
  An Open-Source Tool for CGRA Accelerators
  ☆76Updated 2 months ago
• UCLA-VAST / tapa
  TAPA compiles task-parallel HLS program into high-performance FPGA accelerators. UCLA-maintained.
  ☆176Updated 3 months ago
• pku-dasys / pillars
  An integrated CGRA design framework
  ☆91Updated 8 months ago
• lana555 / dynamatic
  ☆87Updated last year
• UCLA-VAST / AutoSA
  AutoSA: Polyhedral-Based Systolic Array Compiler
  ☆230Updated 2 years ago
• breagen / MachSuite
  Benchmarks for Accelerator Design and Customized Architectures
  ☆135Updated 5 years ago
• tancheng / mlir-cgra
  An MLIR dialect to enable the efficient acceleration of ML model on CGRAs.
  ☆64Updated last year
• UCLA-VAST / AutoBridge
  [FPGA 2021, Best Paper Award] An automated floorplanning and pipelining tool for Vivado HLS.
  ☆127Updated 2 years ago
• StanfordAHA / aha
  ☆61Updated last week
• ucb-bar / constellation
  A Chisel RTL generator for network-on-chip interconnects
  ☆223Updated 3 weeks ago
• pnnl / soda-opt
  ☆53Updated 5 months ago
• tancheng / VectorCGRA
  CGRA framework with vectorization support.
  ☆41Updated last week
• ecolab-nus / morpher-v2
  An Open-Source Tool for CGRA Accelerators
  ☆25Updated 2 months ago
• PrincetonUniversity / muchiSim
  Simulator framework for analysis of performance, energy consumption, area and cost of multi-node multi-chiplet tile-based manycore design…
  ☆72Updated last year
• MPSLab-ASU / ccf
  CGRA Compilation Framework
  ☆88Updated 2 years ago
• esl-epfl / OpenEdgeCGRA
  An Open-Hardware CGRA for accelerated computation on the edge.
  ☆38Updated last month
• cornell-zhang / rosetta
  Rosetta: A Realistic High-level Synthesis Benchmark Suite for Software Programmable FPGAs (FPGA'18)
  ☆168Updated 2 years ago
• UIUC-ChenLab / scalehls
  A scalable High-Level Synthesis framework on MLIR
  ☆284Updated last year
• cwfletcher / buffets
  Implementations of Buffets, which are efficient, composable idioms for implementing Explicit Decoupled Data Orchestration.
  ☆82Updated 6 years ago
• UIUC-ChenLab / ScaleHLS-HIDA
  ☆61Updated 8 months ago
• hngenc / systolic-array
  A DSL for Systolic Arrays
  ☆82Updated 6 years ago
• seldridge / rocket-rocc-examples
  Tests for example Rocket Custom Coprocessors
  ☆75Updated 5 years ago
• NVlabs / matchlib
  SystemC/C++ library of commonly-used hardware functions and components for HLS.
  ☆287Updated last month
• StanfordAHA / garnet
  Next generation CGRA generator
  ☆116Updated this week
• HewlettPackard / mcpat
  An integrated power, area, and timing modeling framework for multicore and manycore architectures
  ☆206Updated 5 years ago
• TeCSAR-UNCC / gem5-SALAM
  ☆107Updated last year
• harvard-acc / gem5-aladdin
  End-to-end SoC simulation: integrating the gem5 system simulator with the Aladdin accelerator simulator.
  ☆254Updated 3 years ago
• CMU-SAFARI / PiDRAM
  PiDRAM is the first flexible end-to-end framework that enables system integration studies and evaluation of real Processing-using-Memory …
  ☆71Updated last year