Alternatives and similar repositories for spatial:

Users that are interested in spatial are comparing it to the libraries listed below

• stanford-ppl / spatial-lang
  Spatial: "Specify Parameterized Accelerators Through Inordinately Abstract Language"
  ☆101Updated 6 years ago
• ucb-bar / midas
  FPGA-Accelerated Simulation Framework Automatically Transforming Arbitrary RTL
  ☆100Updated 5 years ago
• bu-icsg / dana
  Dynamically Allocated Neural Network Accelerator for the RISC-V Rocket Microprocessor in Chisel
  ☆210Updated 5 years ago
• cornell-zhang / heterocl
  HeteroCL: A Multi-Paradigm Programming Infrastructure for Software-Defined Heterogeneous Computing
  ☆334Updated 11 months ago
• scale-lab / la-core
  Linear algebra accelerators for RISC-V (published in ICCD 17)
  ☆66Updated 7 years ago
• chipsalliance / treadle
  Chisel/Firrtl execution engine
  ☆153Updated 7 months ago
• cucapra / dahlia
  Time-sensitive affine types for predictable hardware generation
  ☆142Updated 8 months ago
• ucb-bar / dsptools
  A Library of Chisel3 Tools for Digital Signal Processing
  ☆234Updated 11 months ago
• stanford-ppl / spatial-quickstart
  Quickstart for Spatial language
  ☆34Updated 4 years ago
• NVlabs / matchlib
  SystemC/C++ library of commonly-used hardware functions and components for HLS.
  ☆265Updated 4 months ago
• ucb-bar / hwacha
  Microarchitecture implementation of the decoupled vector-fetch accelerator
  ☆151Updated last year
• bespoke-silicon-group / bsg_manycore
  Tile based architecture designed for computing efficiency, scalability and generality
  ☆248Updated 3 weeks ago
• EECS-NTNU / bismo
  BISMO: A Scalable Bit-Serial Matrix Multiplication Overlay for Reconfigurable Computing
  ☆135Updated 5 years ago
• Xilinx / HLS
  Vitis HLS LLVM source code and examples
  ☆383Updated 5 months ago
• UCLA-VAST / AutoSA
  AutoSA: Polyhedral-Based Systolic Array Compiler
  ☆215Updated 2 years ago
• UCSBarchlab / PyRTL
  A collection of classes providing simple hardware specification, simulation, tracing, and testing suitable for teaching and research. Si…
  ☆269Updated this week
• soDLA-publishment / soDLA
  Chisel implementation of the NVIDIA Deep Learning Accelerator (NVDLA), with self-driving accelerated
  ☆229Updated last month
• maltanar / fpga-tidbits
  Chisel components for FPGA projects
  ☆122Updated last year
• cornell-brg / pymtl
  Python-based hardware modeling framework
  ☆239Updated 5 years ago
• phanrahan / magma
  magma circuits
  ☆259Updated 5 months ago
• tenstorrent / riscv-ocelot
  Ocelot: The Berkeley Out-of-Order Machine With V-EXT support
  ☆157Updated 2 months ago
• firesim / FireMarshal
  Software workload management tool for RISC-V based SoC research. This is the default workload management tool for Chipyard and FireSim.
  ☆79Updated 3 months ago
• chipsalliance / firrtl
  Flexible Intermediate Representation for RTL
  ☆739Updated 7 months ago
• harvard-acc / gem5-aladdin
  End-to-end SoC simulation: integrating the gem5 system simulator with the Aladdin accelerator simulator.
  ☆230Updated 2 years ago
• CSL-KU / firesim-nvdla
  FireSim-NVDLA: NVIDIA Deep Learning Accelerator (NVDLA) Integrated with RISC-V Rocket Chip SoC Running on the Amazon FPGA Cloud
  ☆161Updated 3 years ago
• nvdla / vp
  Virtual Platform for NVDLA
  ☆142Updated 6 years ago
• cornell-zhang / rosetta
  Rosetta: A Realistic High-level Synthesis Benchmark Suite for Software Programmable FPGAs
  ☆164Updated last year
• StanfordAHA / Halide-to-Hardware_archive
  ☆81Updated last month
• cpc / openasip
  Open Application-Specific Instruction Set processor tools (OpenASIP)
  ☆153Updated 2 weeks ago
• OPAE / intel-fpga-bbb
  Basic Building Blocks (BBB) for OPAE-managed Intel FPGAs
  ☆104Updated 2 months ago