PolyArch / dsa-framework
Release of stream-specialization software/hardware stack.
☆116Updated last year
Related projects ⓘ
Alternatives and complementary repositories for dsa-framework
- ☆84Updated 9 months ago
- An integrated CGRA design framework☆83Updated last week
- EQueue Dialect☆39Updated 2 years ago
- Implementations of Buffets, which are efficient, composable idioms for implementing Explicit Decoupled Data Orchestration.☆63Updated 5 years ago
- CGRA-Flow is an integrated framework for CGRA compilation, exploration, synthesis, and development.☆113Updated last week
- Benchmarks for Accelerator Design and Customized Architectures☆116Updated 4 years ago
- A scheduler for spatial DNN accelerators that generate high-performance schedules in one shot using mixed integer programming (MIP)☆74Updated last year
- An LLVM pass that can generate CDFG and map the target loops onto a parameterizable CGRA.☆56Updated last month
- CGRA Compilation Framework☆81Updated last year
- An Open-Source Tool for CGRA Accelerators☆57Updated 3 months ago
- MAERI: A DNN accelerator with reconfigurable interconnects to support flexible dataflow (http://synergy.ece.gatech.edu/tools/maeri/)☆59Updated 3 years ago
- agile hardware-software co-design☆46Updated 2 years ago
- High-Performance Sparse Linear Algebra on HBM-Equipped FPGAs Using HLS☆80Updated last month
- OpenCGRA is an open-source framework for modeling, testing, and evaluating CGRAs.☆135Updated last year
- Tool for optimize CNN blocking☆93Updated 4 years ago
- ☆36Updated 8 months ago
- Simulator framework for analysis of performance, energy consumption, area and cost of multi-node multi-chiplet tile-based manycore design…☆46Updated 4 months ago
- An MLIR dialect to enable the efficient acceleration of ML model on CGRAs.☆53Updated last month
- ☆25Updated 3 years ago
- An analytical framework that models hardware dataflow of tensor applications on spatial architectures using the relation-centric notation…☆80Updated 6 months ago
- dMazeRunner: Dataflow acceleration optimization infrastructure for coarse-grained programmable accelerators☆44Updated 2 years ago
- ☆51Updated this week
- A DSL for Systolic Arrays☆78Updated 5 years ago
- RTL implementation of Flex-DPE.☆91Updated 4 years ago
- ArchExplorer: Microarchitecture Exploration Via Bottleneck Analysis☆30Updated 9 months ago
- An FPGA accelerator for general-purpose Sparse-Matrix Dense-Matrix Multiplication (SpMM).☆71Updated 3 months ago
- RapidStream TAPA compiles task-parallel HLS program into high-frequency FPGA accelerators.☆156Updated this week
- A systolic array simulator for multi-cycle MACs and varying-byte words, with the paper accepted to HPCA 2022.☆65Updated 3 years ago
- End-to-end SoC simulation: integrating the gem5 system simulator with the Aladdin accelerator simulator.☆220Updated 2 years ago
- A scalable High-Level Synthesis framework on MLIR☆228Updated 6 months ago