MPSLab-ASU / DiRACLinks
Dynamically Reconfigurable Architecture Template and Cycle-level Microarchitecture Simulator for Dataflow AcCelerators
☆29Updated 2 years ago
Alternatives and similar repositories for DiRAC
Users that are interested in DiRAC are comparing it to the libraries listed below
Sorting:
- dMazeRunner: Dataflow acceleration optimization infrastructure for coarse-grained programmable accelerators☆47Updated 3 years ago
- MAERI: A DNN accelerator with reconfigurable interconnects to support flexible dataflow (http://synergy.ece.gatech.edu/tools/maeri/)☆66Updated 4 years ago
- HLS project modeling various sparse accelerators.☆12Updated 3 years ago
- A reference implementation of the Mind Mappings Framework.☆30Updated 3 years ago
- ☆61Updated last week
- ☆72Updated 2 years ago
- A systolic array simulator for multi-cycle MACs and varying-byte words, with the paper accepted to HPCA 2022.☆80Updated 3 years ago
- Domain-Specific Architecture Generator 2☆21Updated 3 years ago
- ☆25Updated last year
- DASS HLS Compiler☆29Updated last year
- PAAS: A System Level Simulator for Heterogeneous (CPU-FPGA) Computing Systems☆43Updated 4 years ago
- High-Performance Sparse Linear Algebra on HBM-Equipped FPGAs Using HLS☆95Updated last year
- PARADE: A Cycle-Accurate Full-System Simulation Platform for Accelerator-Rich Architectural Design and Exploration☆49Updated 3 years ago
- ☆15Updated 5 years ago
- PiDRAM is the first flexible end-to-end framework that enables system integration studies and evaluation of real Processing-using-Memory …