Dynamically Reconfigurable Architecture Template and Cycle-level Microarchitecture Simulator for Dataflow AcCelerators
☆30Jul 17, 2023Updated 2 years ago
Alternatives and similar repositories for DiRAC
Users that are interested in DiRAC are comparing it to the libraries listed below
Sorting:
- dMazeRunner: Dataflow acceleration optimization infrastructure for coarse-grained programmable accelerators☆47Apr 4, 2022Updated 3 years ago
- CGRA Compilation Framework☆91Jul 15, 2023Updated 2 years ago
- An integrated CGRA design framework☆91Mar 18, 2025Updated 11 months ago
- Heterogenous ML accelerator☆20May 5, 2025Updated 9 months ago
- OpenCGRA is an open-source framework for modeling, testing, and evaluating CGRAs.☆168Mar 2, 2023Updated 2 years ago
- Netrace: a network packet trace reader☆14Jun 16, 2014Updated 11 years ago
- An Open-Source Tool for CGRA Accelerators☆30Sep 12, 2025Updated 5 months ago
- A low power platform based on X-HEEP and integrating the ESL-CGRA☆17Nov 12, 2025Updated 3 months ago
- NPUsim: Full-Model, Cycle-Level, and Value-Aware Simulator for DNN Accelerators☆49Jan 2, 2025Updated last year
- ☆29Oct 20, 2019Updated 6 years ago
- A portable framework to map DFG (dataflow graph, representing an application) on spatial accelerators.☆40Oct 31, 2022Updated 3 years ago
- Next generation CGRA generator☆118Feb 14, 2026Updated 2 weeks ago
- Release of stream-specialization software/hardware stack.☆120May 5, 2023Updated 2 years ago
- ☆109Feb 12, 2024Updated 2 years ago
- Coarse Grained Reconfigurable Array☆20Feb 18, 2026Updated last week
- A reference implementation of the Mind Mappings Framework.☆30Dec 2, 2021Updated 4 years ago
- Tool for optimize CNN blocking☆95Mar 22, 2020Updated 5 years ago
- Code released to accompany the ISCA paper: "T4: Compiling Sequential Code for Effective Speculative Parallelization in Hardware"☆28Feb 18, 2022Updated 4 years ago
- Python implementations of fixed size hardware types (Bit, BitVector, UInt, SInt, ...) based on the SMT-LIB2 semantics☆18Sep 13, 2023Updated 2 years ago
- An Open-Source Tool for CGRA Accelerators☆82Sep 11, 2025Updated 5 months ago
- ☆13Jan 8, 2020Updated 6 years ago
- CGRA-Flow is an integrated framework for CGRA compilation, exploration, synthesis, and development.☆154Feb 18, 2026Updated last week
- Linux docker for the DNN accelerator exploration infrastructure composed of Accelergy and Timeloop☆62Oct 14, 2025Updated 4 months ago
- A scheduler for spatial DNN accelerators that generate high-performance schedules in one shot using mixed integer programming (MIP)☆85Aug 28, 2023Updated 2 years ago
- HierCGRA: An Open-Source Framework for Large-Scale CGRA with Hierarchical Modeling and Automated Exploration☆14Mar 6, 2023Updated 2 years ago
- An MLIR dialect to enable the efficient acceleration of ML model on CGRAs.☆65Oct 9, 2024Updated last year
- A Reconfigurable Accelerator with Data Reordering Support for Low-Cost On-Chip Dataflow Switching☆76Updated this week
- ☆62Updated this week
- mRNA☆26Mar 16, 2021Updated 4 years ago
- Domain-Specific Architecture Generator 2☆22Oct 2, 2022Updated 3 years ago
- Accelergy is an energy estimation infrastructure for accelerator energy estimations☆156May 26, 2025Updated 9 months ago
- Network on Chip for MPSoC☆28Jan 27, 2026Updated last month
- Matrix Accelerator Generator for GeMM Operations based on SIGMA Architecture in CHISEL HDL☆15Mar 21, 2024Updated last year
- Computational Memory Neural Network Compiler☆11Aug 11, 2021Updated 4 years ago
- Fork of the gem5 simulator with Garnet2.0 and DSENT extensions☆13Jan 28, 2019Updated 7 years ago
- ☆11Aug 4, 2022Updated 3 years ago
- The Chronos FPGA Framework to accelerate ordered applications☆22May 20, 2020Updated 5 years ago
- STONNE: A Simulation Tool for Neural Networks Engines☆147Jun 16, 2025Updated 8 months ago
- ☆71Mar 22, 2020Updated 5 years ago