MPSLab-ASU / DiRACLinks
Dynamically Reconfigurable Architecture Template and Cycle-level Microarchitecture Simulator for Dataflow AcCelerators
☆30Updated 2 years ago
Alternatives and similar repositories for DiRAC
Users that are interested in DiRAC are comparing it to the libraries listed below
Sorting:
- dMazeRunner: Dataflow acceleration optimization infrastructure for coarse-grained programmable accelerators☆47Updated 3 years ago
- MAERI: A DNN accelerator with reconfigurable interconnects to support flexible dataflow (http://synergy.ece.gatech.edu/tools/maeri/)☆65Updated 4 years ago
- A systolic array simulator for multi-cycle MACs and varying-byte words, with the paper accepted to HPCA 2022.☆82Updated 4 years ago
- HLS project modeling various sparse accelerators.☆12Updated 3 years ago
- Domain-Specific Architecture Generator 2☆21Updated 3 years ago
- ☆32Updated last year
- High-Performance Sparse Linear Algebra on HBM-Equipped FPGAs Using HLS☆96Updated last year
- A reference implementation of the Mind Mappings Framework.☆30Updated 4 years ago
- FlexASR: A Reconfigurable Hardware Accelerator for Attention-based Seq-to-Seq Networks☆49Updated 9 months ago
- ☆37Updated 4 years ago
- ☆72Updated 2 years ago
- A fast, accurate trace-based simulator for High-Level Synthesis.☆72Updated 8 months ago
- A DSL for Systolic Arrays☆82Updated 6 years ago
- Lab code for three-day lecture, "Designing CNN Accelerators using Bluespec System Verilog", given at SNU in December 2017☆31Updated 7 years ago
- An example of using Ramulator as memory model in a cycle-accurate SystemC Design☆55Updated 8 years ago
- ☆25Updated last year
- ☆29Updated 8 years ago
- STONNE Simulator integrated into SST Simulator☆22Updated last year
- PARADE: A Cycle-Accurate Full-System Simulation Platform for Accelerator-Rich Architectural Design and Exploration☆48Updated 3 years ago
- ☆16Updated 3 years ago
- A scheduler for spatial DNN accelerators that generate high-performance schedules in one shot using mixed integer programming (MIP)☆83Updated 2 years ago
- ☆39Updated 8 months ago
- NeuroSpector: Dataflow and Mapping Optimizer for Deep Neural Network Accelerators☆21Updated 8 months ago
- An MLIR dialect to enable the efficient acceleration of ML model on CGRAs.☆64Updated last year
- ☆61Updated this week
- Heterogenous ML accelerator☆19Updated 6 months ago
- An FPGA accelerator for general-purpose Sparse-Matrix Dense-Matrix Multiplication (SpMM).☆91Updated last year
- cycle accurate Network-on-Chip Simulator☆31Updated 2 years ago
- ☆42Updated last year
- NeuraChip Accelerator Simulator☆15Updated last year