MPSLab-ASU / DiRACLinks
Dynamically Reconfigurable Architecture Template and Cycle-level Microarchitecture Simulator for Dataflow AcCelerators
☆28Updated 2 years ago
Alternatives and similar repositories for DiRAC
Users that are interested in DiRAC are comparing it to the libraries listed below
Sorting:
- dMazeRunner: Dataflow acceleration optimization infrastructure for coarse-grained programmable accelerators☆46Updated 3 years ago
- MAERI: A DNN accelerator with reconfigurable interconnects to support flexible dataflow (http://synergy.ece.gatech.edu/tools/maeri/)☆64Updated 3 years ago
- A systolic array simulator for multi-cycle MACs and varying-byte words, with the paper accepted to HPCA 2022.☆80Updated 3 years ago
- ☆72Updated 2 years ago
- A reference implementation of the Mind Mappings Framework.☆30Updated 3 years ago
- CGRA Compilation Framework☆84Updated 2 years ago
- High-Performance Sparse Linear Algebra on HBM-Equipped FPGAs Using HLS☆94Updated 10 months ago
- ☆25Updated last year
- Implementations of Buffets, which are efficient, composable idioms for implementing Explicit Decoupled Data Orchestration.☆76Updated 6 years ago
- Documentation for the entire CGRAFlow☆19Updated 3 years ago
- A scheduler for spatial DNN accelerators that generate high-performance schedules in one shot using mixed integer programming (MIP)☆82Updated last year
- FlexASR: A Reconfigurable Hardware Accelerator for Attention-based Seq-to-Seq Networks☆46Updated 5 months ago
- DASS HLS Compiler☆29Updated last year
- ☆27Updated 5 years ago
- A fast, accurate trace-based simulator for High-Level Synthesis.☆67Updated 4 months ago
- HLS project modeling various sparse accelerators.☆13Updated 3 years ago
- PARADE: A Cycle-Accurate Full-System Simulation Platform for Accelerator-Rich Architectural Design and Exploration☆48Updated 3 years ago
- Domain-Specific Architecture Generator 2☆21Updated 2 years ago
- Heterogenous ML accelerator☆18Updated 2 months ago
- ☆60Updated 3 months ago
- ☆10Updated 2 years ago
- ☆36Updated 4 years ago
- PiDRAM is the first flexible end-to-end framework that enables system integration studies and evaluation of real Processing-using-Memory …☆68Updated last year
- A graph linear algebra overlay☆51Updated 2 years ago
- A general framework for optimizing DNN dataflow on systolic array☆39Updated 4 years ago
- ☆58Updated 2 years ago
- [DAC 2020] Analysis and Optimization of the Implicit Broadcasts in FPGA HLS to Improve Maximum Frequency☆32Updated 4 years ago
- ☆30Updated 6 years ago
- A Spatial Accelerator Generation Framework for Tensor Algebra.☆58Updated 3 years ago
- An FPGA accelerator for general-purpose Sparse-Matrix Dense-Matrix Multiplication (SpMM).☆81Updated last year