StanfordAHA / CGRAFlowDocLinks
Documentation for the entire CGRAFlow
☆19Updated 3 years ago
Alternatives and similar repositories for CGRAFlowDoc
Users that are interested in CGRAFlowDoc are comparing it to the libraries listed below
Sorting:
- Dynamically Reconfigurable Architecture Template and Cycle-level Microarchitecture Simulator for Dataflow AcCelerators☆28Updated last year
- ☆27Updated 5 years ago
- ☆15Updated 2 years ago
- dMazeRunner: Dataflow acceleration optimization infrastructure for coarse-grained programmable accelerators☆45Updated 3 years ago
- An example of using Ramulator as memory model in a cycle-accurate SystemC Design☆50Updated 7 years ago
- Integration test for entire CGRA flow☆12Updated 5 years ago
- A SystemC + DRAMSim2 simulator for exploring the SpMV hardware accelerator design space.☆14Updated 10 years ago
- CNN accelerator☆27Updated 7 years ago
- A 32-bit RISC-V Processor Designed with High-Level Synthesis☆52Updated 5 years ago
- Fast, Accurate and Convenient Light-Weight HLS Framework for Academic Design Space Exploration and Evaluation. (LLVM-11)☆60Updated 3 years ago
- ☆71Updated 2 years ago
- Binary Single Precision Floating-point Fused Multiply-Add Unit Design (Verilog HDL)☆19Updated 11 years ago
- CHIPKIT: An agile, reusable open-source framework for rapid test chip development☆41Updated 5 years ago
- Provides the hardware code for the paper "EBPC: Extended Bit-Plane Compression for Deep Neural Network Inference and Training Accelerator…☆24Updated 4 years ago
- ☆16Updated 7 years ago
- ☆35Updated 4 years ago
- ☆59Updated last month
- Contains FPGA benchmarks for Vivado HLS and Catapult HLS☆26Updated 4 years ago
- ☆13Updated 4 years ago
- ☆11Updated last month
- ☆15Updated 2 years ago
- ☆15Updated 6 years ago
- Stencil with Optimized Dataflow Architecture Compiler☆16Updated 5 years ago
- ☆29Updated 6 years ago
- An MLIR dialect to enable the efficient acceleration of ML model on CGRAs.☆59Updated 7 months ago
- [DAC 2020] Analysis and Optimization of the Implicit Broadcasts in FPGA HLS to Improve Maximum Frequency☆32Updated 4 years ago
- DASS HLS Compiler☆29Updated last year
- Hi-DMM: High-Performance Dynamic Memory Management in HLS (High-Level Synthesis)☆25Updated 6 years ago
- Lab code for three-day lecture, "Designing CNN Accelerators using Bluespec System Verilog", given at SNU in December 2017☆29Updated 6 years ago
- CGRA framework with vectorization support.☆30Updated 3 weeks ago