Alternatives and similar repositories for CGRAFlowDoc:

Users that are interested in CGRAFlowDoc are comparing it to the libraries listed below

• StanfordAHA / CGRAFlow
  Integration test for entire CGRA flow
  ☆12Updated 5 years ago
• hyoukjun / microswitch-noc
  ☆24Updated 5 years ago
• whatmough / CHIPKIT
  CHIPKIT: An agile, reusable open-source framework for rapid test chip development
  ☆40Updated 4 years ago
• kkiningh / cs231n-project
  CNN accelerator
  ☆27Updated 7 years ago
• MPSLab-ASU / DiRAC
  Dynamically Reconfigurable Architecture Template and Cycle-level Microarchitecture Simulator for Dataflow AcCelerators
  ☆28Updated last year
• sld-columbia / hl5
  A 32-bit RISC-V Processor Designed with High-Level Synthesis
  ☆50Updated 4 years ago
• cornell-brg / pymtl3-net
  Project repo for the POSH on-chip network generator
  ☆43Updated last year
• Licheng-Guo / vivado-hls-broadcast-optimization
  [DAC 2020] Analysis and Optimization of the Implicit Broadcasts in FPGA HLS to Improve Maximum Frequency
  ☆32Updated 3 years ago
• MPSLab-ASU / dMazeRunner
  dMazeRunner: Dataflow acceleration optimization infrastructure for coarse-grained programmable accelerators
  ☆45Updated 2 years ago
• template-hls / template-hls-float
  ☆27Updated 5 years ago
• maltanar / spmvaccsim
  A SystemC + DRAMSim2 simulator for exploring the SpMV hardware accelerator design space.
  ☆14Updated 10 years ago
• Liu-Cheng / cycle-accurate-SystemC-simulator-over-ramulator
  An example of using Ramulator as memory model in a cycle-accurate SystemC Design
  ☆48Updated 7 years ago
• KastnerRG / Spector-HLS
  Contains FPGA benchmarks for Vivado HLS and Catapult HLS
  ☆26Updated 4 years ago
• chipsalliance / aib-protocols
  ☆25Updated 10 months ago
• gilani / fpfma
  Binary Single Precision Floating-point Fused Multiply-Add Unit Design (Verilog HDL)
  ☆17Updated 11 years ago
• UIUC-ChenLab / rip
  ☆16Updated 6 years ago
• aravinds92 / Systolic-Array
  Systolic array based hardware for Image processing on the SPARTAN-6 FPGA
  ☆12Updated 8 years ago
• jianyicheng / DSS
  DASS HLS Compiler
  ☆27Updated last year
• esl-epfl / OpenEdgeCGRA
  An Open-Hardware CGRA for accelerated computation on the edge.
  ☆13Updated 4 months ago
• ic-lab-duth / NoCpad
  HLS for Networks-on-Chip
  ☆32Updated 3 years ago
• hyoukjun / OpenSMART
  Public release
  ☆49Updated 5 years ago
• hyoukjun / MAESTRO
  MAESTRO binary release
  ☆22Updated 5 years ago
• freecores / robust_axi_fabric
  Generic AXI interconnect fabric
  ☆13Updated 10 years ago
• pulp-platform / hwpe-stream
  IPs for data-plane integration of Hardware Processing Engines (HWPEs) within a PULP system
  ☆18Updated 3 months ago
• icgrp / hipr
  ☆15Updated last year
• zslwyuan / Light-HLS
  Fast, Accurate and Convenient Light-Weight HLS Framework for Academic Design Space Exploration and Evaluation. (LLVM-11)
  ☆58Updated 2 years ago
• UCLA-VAST / FlexCNN
  ☆71Updated last year
• pulp-platform / stream-ebpc
  Provides the hardware code for the paper "EBPC: Extended Bit-Plane Compression for Deep Neural Network Inference and Training Accelerator…
  ☆24Updated 4 years ago