TeCSAR-UNCC / gem5-SALAMLinks
☆92Updated last year
Alternatives and similar repositories for gem5-SALAM
Users that are interested in gem5-SALAM are comparing it to the libraries listed below
Sorting:
- Release of stream-specialization software/hardware stack.☆122Updated 2 years ago
- Implementations of Buffets, which are efficient, composable idioms for implementing Explicit Decoupled Data Orchestration.☆75Updated 6 years ago
- Simulator framework for analysis of performance, energy consumption, area and cost of multi-node multi-chiplet tile-based manycore design…☆68Updated last year
- CGRA Compilation Framework☆85Updated last year
- The gem5-X open source framework (based on the gem5 simulator)☆41Updated 2 years ago
- gem5 repository to study chiplet-based systems☆76Updated 6 years ago
- Benchmarks for Accelerator Design and Customized Architectures☆125Updated 5 years ago
- High-Performance Sparse Linear Algebra on HBM-Equipped FPGAs Using HLS☆93Updated 9 months ago
- An MLIR dialect to enable the efficient acceleration of ML model on CGRAs.☆59Updated 9 months ago
- Fast and accurate DRAM power and energy estimation tool☆168Updated last week
- ☆55Updated 3 months ago
- MultiPIM: A Detailed and Configurable Multi-Stack Processing-In-Memory Simulator☆55Updated 4 years ago
- PARADE: A Cycle-Accurate Full-System Simulation Platform for Accelerator-Rich Architectural Design and Exploration☆48Updated 3 years ago
- EQueue Dialect☆40Updated 3 years ago
- MAERI: A DNN accelerator with reconfigurable interconnects to support flexible dataflow (http://synergy.ece.gatech.edu/tools/maeri/)☆65Updated 3 years ago
- agile hardware-software co-design☆50Updated 3 years ago
- PiDRAM is the first flexible end-to-end framework that enables system integration studies and evaluation of real Processing-using-Memory …☆69Updated last year
- dMazeRunner: Dataflow acceleration optimization infrastructure for coarse-grained programmable accelerators☆45Updated 3 years ago
- ArchExplorer: Microarchitecture Exploration Via Bottleneck Analysis☆32Updated last year
- A scheduler for spatial DNN accelerators that generate high-performance schedules in one shot using mixed integer programming (MIP)☆82Updated last year
- ☆25Updated last year
- An LLVM pass that can generate CDFG and map the target loops onto a parameterizable CGRA.☆73Updated this week
- A speculative mechanism to accelerate long-latency off-chip load requests by removing on-chip cache access latency from their critical pa…☆71Updated 10 months ago
- DAMOV is a benchmark suite and a methodical framework targeting the study of data movement bottlenecks in modern applications. It is inte…☆83Updated last year
- End-to-end SoC simulation: integrating the gem5 system simulator with the Aladdin accelerator simulator.☆240Updated 2 years ago
- ☆30Updated 8 months ago
- mNPUsim: A Cycle-accurate Multi-core NPU Simulator (IISWC 2023)☆58Updated 7 months ago
- Heterogeneous simulator for DECADES Project☆32Updated last year
- A pre-RTL, power-performance model for fixed-function accelerators☆177Updated last year
- A DSL for Systolic Arrays☆80Updated 6 years ago