StanfordAHA / garnetLinks
Next generation CGRA generator
☆116Updated last week
Alternatives and similar repositories for garnet
Users that are interested in garnet are comparing it to the libraries listed below
Sorting:
- ☆61Updated this week
- ☆87Updated last year
- A 32-bit RISC-V Processor Designed with High-Level Synthesis☆54Updated 5 years ago
- An open source high level synthesis (HLS) tool built on top of LLVM☆126Updated last year
- Project repo for the POSH on-chip network generator☆52Updated 8 months ago
- A GPU acceleration flow for RTL simulation with batch stimulus☆116Updated last year
- [FPGA 2021, Best Paper Award] An automated floorplanning and pipelining tool for Vivado HLS.☆127Updated 2 years ago
- CGRA-Flow is an integrated framework for CGRA compilation, exploration, synthesis, and development.☆145Updated 2 weeks ago
- ☆104Updated 3 years ago
- [FPGA 2022, Best Paper Award] Parallel placement and routing of Vivado HLS dataflow designs.☆126Updated 2 years ago
- high-performance RTL simulator☆182Updated last year
- A DSL for Systolic Arrays☆82Updated 6 years ago
- An LLVM pass that can generate CDFG and map the target loops onto a parameterizable CGRA.☆80Updated this week
- DASS HLS Compiler☆29Updated 2 years ago
- Fork of seldridge/rocket-rocc-examples with tests for a systolic array based matmul accelerator☆60Updated 5 months ago
- Tests for example Rocket Custom Coprocessors☆75Updated 5 years ago
- The Task Parallel System Composer (TaPaSCo)☆113Updated last week
- Matchlib Connections Library - latency insensitive channels (from NVlabs/matchlib/connections)☆43Updated 2 weeks ago
- Fast, Accurate and Convenient Light-Weight HLS Framework for Academic Design Space Exploration and Evaluation. (LLVM-11)☆62Updated 3 years ago
- PACoGen: Posit Arithmetic Core Generator☆74Updated 6 years ago
- OpenCGRA is an open-source framework for modeling, testing, and evaluating CGRAs.☆163Updated 2 years ago
- Heterogeneous Research Platform (HERO) for exploration of heterogeneous computers consisting of programmable many-core accelerators and a…☆113Updated 2 years ago
- Rosetta: A Realistic High-level Synthesis Benchmark Suite for Software Programmable FPGAs (FPGA'18)☆168Updated 2 years ago
- A tool to generate optimized hardware files for univariate functions.☆29Updated last year
- SystemC/C++ library of commonly-used hardware functions and components for HLS.☆287Updated last month
- CIRCT-based HLS compilation flows, debugging, and cosimulation tools.☆52Updated 2 years ago
- TAPA compiles task-parallel HLS program into high-performance FPGA accelerators. UCLA-maintained.☆176Updated 3 months ago
- Runtime-First FPGA Interchange Routing Contest @ FPGA’24☆34Updated 6 months ago
- ☆67Updated 2 years ago
- ☆64Updated 7 months ago