StanfordAHA / garnetLinks
Next generation CGRA generator
☆115Updated this week
Alternatives and similar repositories for garnet
Users that are interested in garnet are comparing it to the libraries listed below
Sorting:
- ☆87Updated last year
- A 32-bit RISC-V Processor Designed with High-Level Synthesis☆54Updated 5 years ago
- ☆61Updated last week
- [FPGA 2022, Best Paper Award] Parallel placement and routing of Vivado HLS dataflow designs.☆127Updated 2 years ago
- Matchlib Connections Library - latency insensitive channels (from NVlabs/matchlib/connections)☆43Updated last month
- An open source high level synthesis (HLS) tool built on top of LLVM☆125Updated last year
- Project repo for the POSH on-chip network generator☆51Updated 7 months ago
- CGRA-Flow is an integrated framework for CGRA compilation, exploration, synthesis, and development.☆138Updated 4 months ago
- ☆104Updated 3 years ago
- The Task Parallel System Composer (TaPaSCo)☆110Updated 5 months ago
- A GPU acceleration flow for RTL simulation with batch stimulus☆115Updated last year
- [FPGA 2021, Best Paper Award] An automated floorplanning and pipelining tool for Vivado HLS.☆126Updated 2 years ago
- ☆67Updated 2 years ago
- Heterogeneous Research Platform (HERO) for exploration of heterogeneous computers consisting of programmable many-core accelerators and a…☆112Updated 2 years ago
- Fork of seldridge/rocket-rocc-examples with tests for a systolic array based matmul accelerator☆60Updated 3 months ago
- Rosetta: A Realistic High-level Synthesis Benchmark Suite for Software Programmable FPGAs☆167Updated last year
- An LLVM pass that can generate CDFG and map the target loops onto a parameterizable CGRA.☆74Updated last week
- CGRA framework with vectorization support.☆35Updated this week
- Tests for example Rocket Custom Coprocessors☆75Updated 5 years ago
- OpenCGRA is an open-source framework for modeling, testing, and evaluating CGRAs.☆160Updated 2 years ago
- Linear algebra accelerators for RISC-V (published in ICCD 17)☆67Updated 8 years ago
- Fast, Accurate and Convenient Light-Weight HLS Framework for Academic Design Space Exploration and Evaluation. (LLVM-11)☆62Updated 3 years ago
- Public release☆56Updated 6 years ago
- PACoGen: Posit Arithmetic Core Generator☆75Updated 6 years ago
- Floating point modules for CHISEL☆31Updated 10 years ago
- DASS HLS Compiler☆29Updated 2 years ago
- Meta-Repository for Bespoke Silicon Group's Manycore Architecture (A.K.A HammerBlade)☆43Updated 4 months ago
- Benchmarks for Accelerator Design and Customized Architectures☆130Updated 5 years ago
- This is a Clang tool that parses SystemC models, and synthesizes Verilog from it.☆88Updated last year
- Transactional Verilog design and Verilator Testbench for a RISC-V TensorCore Vector co-processor for reproducible linear algebra☆57Updated 3 years ago