StanfordAHA / garnetLinks
Next generation CGRA generator
☆116Updated this week
Alternatives and similar repositories for garnet
Users that are interested in garnet are comparing it to the libraries listed below
Sorting:
- A 32-bit RISC-V Processor Designed with High-Level Synthesis☆54Updated 5 years ago
- ☆61Updated this week
- An open source high level synthesis (HLS) tool built on top of LLVM☆125Updated last year
- ☆87Updated last year
- [FPGA 2022, Best Paper Award] Parallel placement and routing of Vivado HLS dataflow designs.☆126Updated 2 years ago
- The Task Parallel System Composer (TaPaSCo)☆111Updated 5 months ago
- Matchlib Connections Library - latency insensitive channels (from NVlabs/matchlib/connections)☆43Updated last month
- A GPU acceleration flow for RTL simulation with batch stimulus☆115Updated last year
- CGRA-Flow is an integrated framework for CGRA compilation, exploration, synthesis, and development.☆143Updated this week
- Rosetta: A Realistic High-level Synthesis Benchmark Suite for Software Programmable FPGAs (FPGA'18)☆168Updated 2 years ago
- [FPGA 2021, Best Paper Award] An automated floorplanning and pipelining tool for Vivado HLS.☆126Updated 2 years ago
- Heterogeneous Research Platform (HERO) for exploration of heterogeneous computers consisting of programmable many-core accelerators and a…☆112Updated 2 years ago
- OpenCGRA is an open-source framework for modeling, testing, and evaluating CGRAs.☆161Updated 2 years ago
- An LLVM pass that can generate CDFG and map the target loops onto a parameterizable CGRA.☆78Updated last month
- ☆104Updated 3 years ago
- The OpenPiton Platform☆28Updated 2 years ago
- Project repo for the POSH on-chip network generator☆51Updated 7 months ago
- ☆67Updated 2 years ago
- CIRCT-based HLS compilation flows, debugging, and cosimulation tools.☆51Updated 2 years ago
- Fork of seldridge/rocket-rocc-examples with tests for a systolic array based matmul accelerator☆60Updated 4 months ago
- CGRA framework with vectorization support.☆39Updated this week
- high-performance RTL simulator☆181Updated last year
- Tests for example Rocket Custom Coprocessors☆75Updated 5 years ago
- DASS HLS Compiler☆29Updated 2 years ago
- ☆64Updated 6 months ago
- AXI Adapter(s) for RISC-V Atomic Operations☆66Updated last week
- Runtime-First FPGA Interchange Routing Contest @ FPGA’24☆34Updated 5 months ago
- Benchmarks for Accelerator Design and Customized Architectures☆135Updated 5 years ago
- CHIPKIT: An agile, reusable open-source framework for rapid test chip development☆42Updated 5 years ago
- This is a Clang tool that parses SystemC models, and synthesizes Verilog from it.☆88Updated last year