Alternatives and similar repositories for garnet

Users that are interested in garnet are comparing it to the libraries listed below

• sld-columbia / hl5
  A 32-bit RISC-V Processor Designed with High-Level Synthesis
  ☆54Updated 5 years ago
• lana555 / dynamatic
  ☆86Updated last year
• dillonhuff / ahaHLS
  An open source high level synthesis (HLS) tool built on top of LLVM
  ☆124Updated last year
• cornell-brg / pymtl3-net
  Project repo for the POSH on-chip network generator
  ☆48Updated 3 months ago
• StanfordAHA / aha
  ☆59Updated this week
• hlslibs / matchlib_connections
  Matchlib Connections Library - latency insensitive channels (from NVlabs/matchlib/connections)
  ☆42Updated last month
• UCLA-VAST / RapidStream
  [FPGA 2022, Best Paper Award] Parallel placement and routing of Vivado HLS dataflow designs.
  ☆126Updated 2 years ago
• rdaly525 / coreir
  ☆103Updated 3 years ago
• ucb-bar / gemmini-rocc-tests
  Fork of seldridge/rocket-rocc-examples with tests for a systolic array based matmul accelerator
  ☆59Updated 2 weeks ago
• intel / aib-phy-hardware
  ☆66Updated 2 years ago
• tancheng / VectorCGRA
  CGRA framework with vectorization support.
  ☆32Updated this week
• UCLA-VAST / AutoBridge
  [FPGA 2021, Best Paper Award] An automated floorplanning and pipelining tool for Vivado HLS.
  ☆122Updated 2 years ago
• dian-lun-lin / RTLflow
  A GPU acceleration flow for RTL simulation with batch stimulus
  ☆112Updated last year
• ucsc-vama / essent
  high-performance RTL simulator
  ☆168Updated last year
• tancheng / CGRA-Flow
  CGRA-Flow is an integrated framework for CGRA compilation, exploration, synthesis, and development.
  ☆133Updated 3 weeks ago
• pulp-platform / hero
  Heterogeneous Research Platform (HERO) for exploration of heterogeneous computers consisting of programmable many-core accelerators and a…
  ☆110Updated last year
• pnnl / OpenCGRA
  OpenCGRA is an open-source framework for modeling, testing, and evaluating CGRAs.
  ☆154Updated 2 years ago
• cornell-zhang / rosetta
  Rosetta: A Realistic High-level Synthesis Benchmark Suite for Software Programmable FPGAs
  ☆166Updated last year
• seldridge / rocket-rocc-examples
  Tests for example Rocket Custom Coprocessors
  ☆74Updated 5 years ago
• manish-kj / PACoGen
  PACoGen: Posit Arithmetic Core Generator
  ☆73Updated 5 years ago
• chipsalliance / aib-phy-hardware
  Advanced Interface Bus (AIB) die-to-die hardware open source
  ☆138Updated 9 months ago
• esa-tu-darmstadt / tapasco
  The Task Parallel System Composer (TaPaSCo)
  ☆110Updated last month
• mrc-donato / CHIPKIT-Tutorial
  ☆15Updated 4 years ago
• intel / rapid-design-methods-for-developing-hardware-accelerators
  ☆88Updated 2 years ago
• Xilinx / fpga24_routing_contest
  Runtime-First FPGA Interchange Routing Contest @ FPGA’24
  ☆33Updated last month
• tancheng / CGRA-Mapper
  An LLVM pass that can generate CDFG and map the target loops onto a parameterizable CGRA.
  ☆73Updated this week
• firesim / FireMarshal
  Software workload management tool for RISC-V based SoC research. This is the default workload management tool for Chipyard and FireSim.
  ☆83Updated last month
• circt-hls / circt-hls
  CIRCT-based HLS compilation flows, debugging, and cosimulation tools.
  ☆49Updated last year
• Liu-Cheng / cycle-accurate-SystemC-simulator-over-ramulator
  An example of using Ramulator as memory model in a cycle-accurate SystemC Design
  ☆50Updated 8 years ago
• VeriGOOD-ML / public
  ☆60Updated 2 months ago