pnnl / soda-optLinks
☆47Updated last month
Alternatives and similar repositories for soda-opt
Users that are interested in soda-opt are comparing it to the libraries listed below
Sorting:
- An Open-Source Tool for CGRA Accelerators☆67Updated 3 months ago
- An MLIR dialect to enable the efficient acceleration of ML model on CGRAs.☆60Updated 9 months ago
- ☆56Updated 4 months ago
- An LLVM pass that can generate CDFG and map the target loops onto a parameterizable CGRA.☆74Updated last week
- CGRA-Flow is an integrated framework for CGRA compilation, exploration, synthesis, and development.☆135Updated last month
- An integrated CGRA design framework☆90Updated 4 months ago
- OpenCGRA is an open-source framework for modeling, testing, and evaluating CGRAs.☆155Updated 2 years ago
- An Open-Source Tool for CGRA Accelerators☆23Updated last year
- RapidStream TAPA compiles task-parallel HLS program into high-frequency FPGA accelerators.☆173Updated this week
- ☆60Updated 3 months ago
- ☆30Updated 9 months ago
- A fast, accurate trace-based simulator for High-Level Synthesis.☆67Updated 4 months ago
- A hardware synthesis framework with multi-level paradigm☆40Updated 6 months ago
- ☆59Updated this week
- High-Performance Sparse Linear Algebra on HBM-Equipped FPGAs Using HLS☆94Updated 10 months ago
- A systolic array simulator for multi-cycle MACs and varying-byte words, with the paper accepted to HPCA 2022.☆80Updated 3 years ago
- An open-source parameterizable NPU generator with full-stack multi-target compilation stack for intelligent workloads.☆60Updated 4 months ago
- An Open-Hardware CGRA for accelerated computation on the edge.☆30Updated 10 months ago
- ☆86Updated last year
- CGRA framework with vectorization support.☆33Updated this week
- The RAD flow is an open-source academic architecture exploration and evaluation flow for novel beyond-FPGA reconfigurable acceleration de…☆38Updated 2 weeks ago
- Multi-core HW accelerator mapping optimization framework for layer-fused ML workloads.☆57Updated last month
- CGRA Compilation Framework☆84Updated 2 years ago
- A toolchain for rapid design space exploration of chiplet architectures☆55Updated last week
- An MLIR Complier for PyTorch/C/C++ Codes into HLS Dataflow Designs☆44Updated this week
- Simulator framework for analysis of performance, energy consumption, area and cost of multi-node multi-chiplet tile-based manycore design…☆68Updated last year
- ☆43Updated 10 months ago
- An FPGA accelerator for general-purpose Sparse-Matrix Dense-Matrix Multiplication (SpMM).☆81Updated last year
- ☆58Updated 2 years ago
- The open-sourced version of BOOM-Explorer☆43Updated 2 years ago