pnnl / soda-optLinks
☆53Updated 5 months ago
Alternatives and similar repositories for soda-opt
Users that are interested in soda-opt are comparing it to the libraries listed below
Sorting:
- An Open-Source Tool for CGRA Accelerators☆80Updated 3 months ago
- An MLIR dialect to enable the efficient acceleration of ML model on CGRAs.☆64Updated last year
- An integrated CGRA design framework☆91Updated 9 months ago
- ☆61Updated 9 months ago
- An Open-Source Tool for CGRA Accelerators☆27Updated 3 months ago
- CGRA-Flow is an integrated framework for CGRA compilation, exploration, synthesis, and development.☆149Updated this week
- An LLVM pass that can generate CDFG and map the target loops onto a parameterizable CGRA.☆79Updated last week
- An MLIR Complier for PyTorch/C/C++ Codes into HLS Dataflow Designs☆56Updated 4 months ago
- ☆62Updated last week
- ☆32Updated last year
- TAPA compiles task-parallel HLS program into high-performance FPGA accelerators. UCLA-maintained.☆176Updated 4 months ago
- A fast, accurate trace-based simulator for High-Level Synthesis.☆73Updated last week
- OpenCGRA is an open-source framework for modeling, testing, and evaluating CGRAs.☆164Updated 2 years ago
- A toolchain for rapid design space exploration of chiplet architectures☆70Updated 5 months ago
- A systolic array simulator for multi-cycle MACs and varying-byte words, with the paper accepted to HPCA 2022.☆83Updated 4 years ago
- ☆65Updated 7 months ago
- The RAD flow is an open-source academic architecture exploration and evaluation flow for novel beyond-FPGA reconfigurable acceleration de…☆38Updated 5 months ago
- CGRA Compilation Framework☆89Updated 2 years ago
- High-Performance Sparse Linear Algebra on HBM-Equipped FPGAs Using HLS☆95Updated last year
- ☆87Updated last year
- Multi-core HW accelerator mapping optimization framework for layer-fused ML workloads.☆64Updated 5 months ago
- An FPGA accelerator for general-purpose Sparse-Matrix Dense-Matrix Multiplication (SpMM).☆92Updated last year
- A hardware synthesis framework with multi-level paradigm☆43Updated 11 months ago
- Implementations of Buffets, which are efficient, composable idioms for implementing Explicit Decoupled Data Orchestration.☆81Updated 6 years ago
- Simulator framework for analysis of performance, energy consumption, area and cost of multi-node multi-chiplet tile-based manycore design…☆73Updated last year
- A list of our chiplet simulaters☆45Updated 6 months ago
- An Open-Hardware CGRA for accelerated computation on the edge.☆39Updated last month
- Benchmarks for Accelerator Design and Customized Architectures☆135Updated 5 years ago
- A scheduler for spatial DNN accelerators that generate high-performance schedules in one shot using mixed integer programming (MIP)☆84Updated 2 years ago
- gem5 repository to study chiplet-based systems☆85Updated 6 years ago