pnnl / soda-opt
☆32Updated 2 months ago
Related projects: ⓘ
- An Open-Source Tool for CGRA Accelerators☆50Updated last month
- CGRA-Flow is an integrated framework for CGRA compilation, exploration, synthesis, and development.☆102Updated this week
- ☆33Updated 6 months ago
- An MLIR dialect to enable the efficient acceleration of ML model on CGRAs.☆51Updated 2 weeks ago
- An integrated CGRA design framework☆82Updated 9 months ago
- An LLVM pass that can generate CDFG and map the target loops onto a parameterizable CGRA.☆53Updated this week
- A systolic array simulator for multi-cycle MACs and varying-byte words, with the paper accepted to HPCA 2022.☆60Updated 2 years ago
- gem5 repository to study chiplet-based systems☆63Updated 5 years ago
- Template-based Reconfigurable Architecture Modeling Framework☆13Updated 2 years ago
- ☆86Updated 6 months ago
- Open-source Framework for HPCA2024 paper: Gemini: Mapping and Architecture Co-exploration for Large-scale DNN Chiplet Accelerators☆47Updated 2 weeks ago
- An FPGA accelerator for general-purpose Sparse-Matrix Dense-Matrix Multiplication (SpMM).☆62Updated last month
- A RISC-V BOOM Microarchitecture Power Modeling Framework☆17Updated last year
- Dataset for ML-guided Accelerator Design☆30Updated 5 months ago
- RapidStream-TAPA compiles task-parallel HLS program into high-frequency FPGA accelerators.☆149Updated this week
- CGRA Compilation Framework☆77Updated last year
- OpenCGRA is an open-source framework for modeling, testing, and evaluating CGRAs.☆131Updated last year
- High-Performance Sparse Linear Algebra on HBM-Equipped FPGAs Using HLS☆77Updated last month
- The RAD flow is an open-source academic architecture exploration and evaluation flow for novel beyond-FPGA reconfigurable acceleration de…☆25Updated last week
- A list of our chiplet simulaters☆18Updated 3 years ago
- Implementations of Buffets, which are efficient, composable idioms for implementing Explicit Decoupled Data Orchestration.☆62Updated 5 years ago
- Benchmarks for Accelerator Design and Customized Architectures☆113Updated 4 years ago
- An Automated Framework for Generic Graph Neural Network Accelerator Generation, Simulation, and Optimization☆18Updated 9 months ago
- Simulator framework for analysis of performance, energy consumption, area and cost of multi-node multi-chiplet tile-based manycore design…☆43Updated 2 months ago
- CGRA framework with vectorization support.☆18Updated 5 months ago
- MICRO22 artifact evaluation for Sparseloop☆34Updated 2 years ago
- A dataflow architecture for universal graph neural network inference via multi-queue streaming.☆65Updated last year
- DRA+RISC-V Exploration Framework☆12Updated 8 months ago
- ☆46Updated this week
- A scheduler for spatial DNN accelerators that generate high-performance schedules in one shot using mixed integer programming (MIP)☆73Updated last year