pnnl / soda-optLinks
☆53Updated 4 months ago
Alternatives and similar repositories for soda-opt
Users that are interested in soda-opt are comparing it to the libraries listed below
Sorting:
- An Open-Source Tool for CGRA Accelerators☆76Updated 2 months ago
- An MLIR dialect to enable the efficient acceleration of ML model on CGRAs.☆64Updated last year
- An LLVM pass that can generate CDFG and map the target loops onto a parameterizable CGRA.☆78Updated last month
- ☆60Updated 7 months ago
- CGRA-Flow is an integrated framework for CGRA compilation, exploration, synthesis, and development.☆143Updated this week
- An integrated CGRA design framework☆91Updated 7 months ago
- An Open-Source Tool for CGRA Accelerators☆25Updated 2 months ago
- ☆61Updated this week
- An MLIR Complier for PyTorch/C/C++ Codes into HLS Dataflow Designs☆51Updated 3 months ago
- TAPA compiles task-parallel HLS program into high-performance FPGA accelerators.☆175Updated 3 months ago
- ☆32Updated last year
- OpenCGRA is an open-source framework for modeling, testing, and evaluating CGRAs.☆161Updated 2 years ago
- The RAD flow is an open-source academic architecture exploration and evaluation flow for novel beyond-FPGA reconfigurable acceleration de…☆38Updated 3 months ago
- ☆64Updated 6 months ago
- An Open-Hardware CGRA for accelerated computation on the edge.☆37Updated 2 weeks ago
- An FPGA accelerator for general-purpose Sparse-Matrix Dense-Matrix Multiplication (SpMM).☆91Updated last year
- A fast, accurate trace-based simulator for High-Level Synthesis.☆71Updated 7 months ago
- ☆87Updated last year
- CGRA Compilation Framework☆88Updated 2 years ago
- Simulator framework for analysis of performance, energy consumption, area and cost of multi-node multi-chiplet tile-based manycore design…☆72Updated last year
- A systolic array simulator for multi-cycle MACs and varying-byte words, with the paper accepted to HPCA 2022.☆82Updated 4 years ago
- High-Performance Sparse Linear Algebra on HBM-Equipped FPGAs Using HLS☆95Updated last year
- A toolchain for rapid design space exploration of chiplet architectures☆64Updated 3 months ago
- Multi-core HW accelerator mapping optimization framework for layer-fused ML workloads.☆63Updated 4 months ago
- A hardware synthesis framework with multi-level paradigm☆41Updated 10 months ago
- ☆60Updated 2 years ago
- CHARM: Composing Heterogeneous Accelerators on Heterogeneous SoC Architecture☆159Updated this week
- CGRA framework with vectorization support.☆39Updated this week
- AIM: Accelerating Arbitrary-precision Integer Multiplication on Heterogeneous Reconfigurable Computing Platform Versal ACAP (Full Paper a…☆25Updated 5 months ago
- HW Architecture-Mapping Design Space Exploration Framework for Deep Learning Accelerators☆165Updated 3 weeks ago