PolyArch / dsagen2Links
Domain-Specific Architecture Generator 2
☆21Updated 3 years ago
Alternatives and similar repositories for dsagen2
Users that are interested in dsagen2 are comparing it to the libraries listed below
Sorting:
- Artifact evaluation of PLDI'24 paper "Allo: A Programming Model for Composable Accelerator Design"☆30Updated last year
- dMazeRunner: Dataflow acceleration optimization infrastructure for coarse-grained programmable accelerators☆47Updated 3 years ago
- ☆36Updated 7 months ago
- STONNE Simulator integrated into SST Simulator☆21Updated last year
- A Spatial Accelerator Generation Framework for Tensor Algebra.☆60Updated 3 years ago
- agile hardware-software co-design☆52Updated 3 years ago
- An HBM FPGA based SpMV Accelerator☆17Updated last year
- ☆32Updated last year
- ☆36Updated 4 years ago
- EQueue Dialect☆40Updated 3 years ago
- The simulator for SPADA, an SpGEMM accelerator with adaptive dataflow☆41Updated 2 years ago
- ☆28Updated 2 years ago
- Linux docker for the DNN accelerator exploration infrastructure composed of Accelergy and Timeloop☆58Updated last month
- A reference implementation of the Mind Mappings Framework.☆30Updated 3 years ago
- A scheduler for spatial DNN accelerators that generate high-performance schedules in one shot using mixed integer programming (MIP)☆83Updated 2 years ago
- cycle accurate Network-on-Chip Simulator☆31Updated 2 years ago
- High-Performance Sparse Linear Algebra on HBM-Equipped FPGAs Using HLS☆95Updated last year
- Dynamically Reconfigurable Architecture Template and Cycle-level Microarchitecture Simulator for Dataflow AcCelerators☆30Updated 2 years ago
- DAC'22 paper: "Automated Accelerator Optimization Aided by Graph Neural Networks"☆40Updated 2 years ago
- DOSA: Differentiable Model-Based One-Loop Search for DNN Accelerators☆18Updated last year
- A graph linear algebra overlay☆51Updated 2 years ago
- MAERI: A DNN accelerator with reconfigurable interconnects to support flexible dataflow (http://synergy.ece.gatech.edu/tools/maeri/)☆65Updated 4 years ago
- mNPUsim: A Cycle-accurate Multi-core NPU Simulator (IISWC 2023)☆65Updated 2 weeks ago
- Fibertree emulator☆15Updated last year
- H2-LLM: Hardware-Dataflow Co-Exploration for Heterogeneous Hybrid-Bonding-based Low-Batch LLM Inference☆76Updated 6 months ago
- ☆25Updated last year
- ☆15Updated 3 years ago
- Release of stream-specialization software/hardware stack.☆119Updated 2 years ago
- SimplePIM is the first high-level programming framework for real-world processing-in-memory (PIM) architectures. Described in the PACT 20…☆31Updated 2 years ago
- Artifact for "DX100: A Programmable Data Access Accelerator for Indirection (ISCA 2025)" paper☆13Updated last week