tancheng / CGRA-Bench
☆12Updated 2 years ago
Related projects ⓘ
Alternatives and complementary repositories for CGRA-Bench
- An LLVM pass that can generate CDFG and map the target loops onto a parameterizable CGRA.☆56Updated this week
- An MLIR dialect to enable the efficient acceleration of ML model on CGRAs.☆53Updated last month
- dMazeRunner: Dataflow acceleration optimization infrastructure for coarse-grained programmable accelerators☆44Updated 2 years ago
- Template-based Reconfigurable Architecture Modeling Framework☆13Updated 2 years ago
- CGRA framework with vectorization support.☆19Updated this week
- The programming runtime and interfaces for ARENA.☆14Updated 3 years ago
- A systolic array simulator for multi-cycle MACs and varying-byte words, with the paper accepted to HPCA 2022.☆65Updated 3 years ago
- ☆23Updated 3 years ago
- ☆37Updated 8 months ago
- CGRA-Flow is an integrated framework for CGRA compilation, exploration, synthesis, and development.☆113Updated last week
- ☆84Updated 9 months ago
- EQueue Dialect☆39Updated 2 years ago
- Benchmarks for Accelerator Design and Customized Architectures☆116Updated 4 years ago
- An Open-Source Tool for CGRA Accelerators☆17Updated 7 months ago
- STONNE Simulator integrated into SST Simulator☆17Updated 7 months ago
- ☆10Updated last year
- An Open-Source Tool for CGRA Accelerators☆57Updated 3 months ago
- MAERI: A DNN accelerator with reconfigurable interconnects to support flexible dataflow (http://synergy.ece.gatech.edu/tools/maeri/)☆59Updated 3 years ago
- Implementations of Buffets, which are efficient, composable idioms for implementing Explicit Decoupled Data Orchestration.☆64Updated 5 years ago
- mNPUsim: A Cycle-accurate Multi-core NPU Simulator (IISWC 2023)☆37Updated 6 months ago
- A reference implementation of the Mind Mappings Framework.☆28Updated 2 years ago
- A scheduler for spatial DNN accelerators that generate high-performance schedules in one shot using mixed integer programming (MIP)☆74Updated last year
- ☆25Updated 3 years ago
- Fork of gem5 with support for manycore architectures. Includes models and scripts to evaluate a software-defined-vector architecture.☆11Updated 3 years ago
- [DAC 2020] Analysis and Optimization of the Implicit Broadcasts in FPGA HLS to Improve Maximum Frequency☆32Updated 3 years ago
- High-Performance Sparse Linear Algebra on HBM-Equipped FPGAs Using HLS☆80Updated last month
- An open-source DRAM power model based on extensive experimental characterization of real DRAM modules. Described in the SIGMETRICS 2018 …☆38Updated 5 years ago
- [FPGA'21] Microbenchmarks for Demystifying the Memory System of Modern Datacenter FPGAs for Software Programmers☆29Updated 2 years ago
- CGRA Compilation Framework☆81Updated last year
- Multi-core HW accelerator mapping optimization framework for layer-fused ML workloads.☆40Updated this week