Alternatives and similar repositories for CGRA-Bench:

Users that are interested in CGRA-Bench are comparing it to the libraries listed below

• tancheng / CGRA-Mapper
  An LLVM pass that can generate CDFG and map the target loops onto a parameterizable CGRA.
  ☆67Updated last week
• pku-dasys / pillars
  An integrated CGRA design framework
  ☆87Updated last month
• ecolab-nus / morpher
  An Open-Source Tool for CGRA Accelerators
  ☆64Updated last week
• yhqiu16 / TRAM
  Template-based Reconfigurable Architecture Modeling Framework
  ☆14Updated 2 years ago
• tancheng / mlir-cgra
  An MLIR dialect to enable the efficient acceleration of ML model on CGRAs.
  ☆58Updated 6 months ago
• tancheng / CGRA-Flow
  CGRA-Flow is an integrated framework for CGRA compilation, exploration, synthesis, and development.
  ☆123Updated last week
• tancheng / VectorCGRA
  CGRA framework with vectorization support.
  ☆29Updated this week
• UIUC-ChenLab / ScaleHLS-HIDA
  ☆49Updated last month
• diwu1990 / uSystolic-Sim
  A systolic array simulator for multi-cycle MACs and varying-byte words, with the paper accepted to HPCA 2022.
  ☆74Updated 3 years ago
• andrewboutros / rad-flow
  The RAD flow is an open-source academic architecture exploration and evaluation flow for novel beyond-FPGA reconfigurable acceleration de…
  ☆34Updated 2 weeks ago
• pnnl / soda-opt
  ☆44Updated last month
• pku-liang / Hector
  A hardware synthesis framework with multi-level paradigm
  ☆38Updated 3 months ago
• ecolab-nus / morpher-v2
  An Open-Source Tool for CGRA Accelerators
  ☆21Updated last year
• cornell-brg / pymtl3-net
  Project repo for the POSH on-chip network generator
  ☆45Updated last month
• UCLA-VAST / hbmbench
  ☆23Updated 4 years ago
• UCLA-VAST / FlexCNN
  ☆71Updated 2 years ago
• cornell-zhang / HiSparse
  High-Performance Sparse Linear Algebra on HBM-Equipped FPGAs Using HLS
  ☆90Updated 6 months ago
• rgb000000 / eyeriss-chisel3
  eyeriss-chisel3
  ☆40Updated 2 years ago
• Liu-Cheng / cycle-accurate-SystemC-simulator-over-ramulator
  An example of using Ramulator as memory model in a cycle-accurate SystemC Design
  ☆49Updated 7 years ago
• Licheng-Guo / vivado-hls-broadcast-optimization
  [DAC 2020] Analysis and Optimization of the Implicit Broadcasts in FPGA HLS to Improve Maximum Frequency
  ☆32Updated 4 years ago
• sfu-arch / SpGEMM
  ☆35Updated 4 years ago
• lana555 / dynamatic
  ☆86Updated last year
• StanfordAHA / CGRAFlowDoc
  Documentation for the entire CGRAFlow
  ☆19Updated 3 years ago
• arcade-lab / tia-infrastructure
  ☆18Updated 7 years ago
• MPSLab-ASU / dMazeRunner
  dMazeRunner: Dataflow acceleration optimization infrastructure for coarse-grained programmable accelerators
  ☆45Updated 3 years ago
• hngenc / stellar
  ☆26Updated 5 months ago
• hyoukjun / microswitch-noc
  ☆26Updated 5 years ago
• zslwyuan / Light-HLS
  Fast, Accurate and Convenient Light-Weight HLS Framework for Academic Design Space Exploration and Evaluation. (LLVM-11)
  ☆60Updated 3 years ago
• icgrp / pld2022
  ☆15Updated 2 years ago
• maeri-project / MAERI_bsv
  MAERI: A DNN accelerator with reconfigurable interconnects to support flexible dataflow (http://synergy.ece.gatech.edu/tools/maeri/)
  ☆64Updated 3 years ago