ecolab-nus / morpherLinks
An Open-Source Tool for CGRA Accelerators
☆72Updated last week
Alternatives and similar repositories for morpher
Users that are interested in morpher are comparing it to the libraries listed below
Sorting:
- An integrated CGRA design framework☆91Updated 5 months ago
- ☆49Updated 2 months ago
- CGRA-Flow is an integrated framework for CGRA compilation, exploration, synthesis, and development.☆136Updated 2 months ago
- An Open-Source Tool for CGRA Accelerators☆24Updated last year
- OpenCGRA is an open-source framework for modeling, testing, and evaluating CGRAs.☆158Updated 2 years ago
- TAPA compiles task-parallel HLS program into high-performance FPGA accelerators.☆174Updated 3 weeks ago
- ☆58Updated 5 months ago
- High-Performance Sparse Linear Algebra on HBM-Equipped FPGAs Using HLS☆95Updated 11 months ago
- An LLVM pass that can generate CDFG and map the target loops onto a parameterizable CGRA.☆74Updated 3 weeks ago
- An MLIR dialect to enable the efficient acceleration of ML model on CGRAs.☆61Updated 11 months ago
- A systolic array simulator for multi-cycle MACs and varying-byte words, with the paper accepted to HPCA 2022.☆80Updated 3 years ago
- Implementations of Buffets, which are efficient, composable idioms for implementing Explicit Decoupled Data Orchestration.☆77Updated 6 years ago
- Multi-core HW accelerator mapping optimization framework for layer-fused ML workloads.☆58Updated 2 months ago
- A list of our chiplet simulaters☆37Updated 2 months ago
- MAERI: A DNN accelerator with reconfigurable interconnects to support flexible dataflow (http://synergy.ece.gatech.edu/tools/maeri/)☆64Updated 3 years ago
- A Reconfigurable Accelerator with Data Reordering Support for Low-Cost On-Chip Dataflow Switching☆62Updated 3 weeks ago
- [FPGA 2021, Best Paper Award] An automated floorplanning and pipelining tool for Vivado HLS.☆123Updated 2 years ago
- An MLIR Complier for PyTorch/C/C++ Codes into HLS Dataflow Designs☆47Updated last month
- An Open-Hardware CGRA for accelerated computation on the edge.☆33Updated last year
- A RISC-V BOOM Microarchitecture Power Modeling Framework☆28Updated 2 years ago
- CGRA Compilation Framework☆86Updated 2 years ago
- RTL implementation of Flex-DPE.☆110Updated 5 years ago
- A toolchain for rapid design space exploration of chiplet architectures☆59Updated last month
- AutoSA: Polyhedral-Based Systolic Array Compiler☆223Updated 2 years ago
- ☆31Updated 10 months ago
- An open-source parameterizable NPU generator with full-stack multi-target compilation stack for intelligent workloads.☆63Updated 6 months ago
- Release of stream-specialization software/hardware stack.☆121Updated 2 years ago
- Simulator framework for analysis of performance, energy consumption, area and cost of multi-node multi-chiplet tile-based manycore design…☆69Updated last year
- CHARM: Composing Heterogeneous Accelerators on Heterogeneous SoC Architecture☆154Updated last week
- The open-sourced version of BOOM-Explorer☆43Updated 2 years ago