ecolab-nus / morpherLinks
An Open-Source Tool for CGRA Accelerators
☆76Updated 2 months ago
Alternatives and similar repositories for morpher
Users that are interested in morpher are comparing it to the libraries listed below
Sorting:
- An integrated CGRA design framework☆91Updated 7 months ago
- CGRA-Flow is an integrated framework for CGRA compilation, exploration, synthesis, and development.☆143Updated this week
- ☆53Updated 4 months ago
- An Open-Source Tool for CGRA Accelerators☆25Updated 2 months ago
- OpenCGRA is an open-source framework for modeling, testing, and evaluating CGRAs.☆161Updated 2 years ago
- Simulator framework for analysis of performance, energy consumption, area and cost of multi-node multi-chiplet tile-based manycore design…☆72Updated last year
- ☆60Updated 7 months ago
- CGRA Compilation Framework☆88Updated 2 years ago
- An LLVM pass that can generate CDFG and map the target loops onto a parameterizable CGRA.☆78Updated last month
- High-Performance Sparse Linear Algebra on HBM-Equipped FPGAs Using HLS☆95Updated last year
- An MLIR dialect to enable the efficient acceleration of ML model on CGRAs.☆64Updated last year
- TAPA compiles task-parallel HLS program into high-performance FPGA accelerators.☆175Updated 2 months ago
- The open-sourced version of BOOM-Explorer☆44Updated 2 years ago
- A systolic array simulator for multi-cycle MACs and varying-byte words, with the paper accepted to HPCA 2022.☆82Updated 4 years ago
- MAERI: A DNN accelerator with reconfigurable interconnects to support flexible dataflow (http://synergy.ece.gatech.edu/tools/maeri/)☆65Updated 4 years ago
- A RISC-V BOOM Microarchitecture Power Modeling Framework☆30Updated 2 years ago
- An MLIR Complier for PyTorch/C/C++ Codes into HLS Dataflow Designs☆51Updated 3 months ago
- A Reconfigurable Accelerator with Data Reordering Support for Low-Cost On-Chip Dataflow Switching☆70Updated last week
- The RAD flow is an open-source academic architecture exploration and evaluation flow for novel beyond-FPGA reconfigurable acceleration de…☆38Updated 3 months ago
- CHARM: Composing Heterogeneous Accelerators on Heterogeneous SoC Architecture☆159Updated last week
- Multi-core HW accelerator mapping optimization framework for layer-fused ML workloads.☆63Updated 4 months ago
- ☆32Updated last year
- An Open-Hardware CGRA for accelerated computation on the edge.☆37Updated last week
- A list of our chiplet simulaters☆43Updated 4 months ago
- Release of stream-specialization software/hardware stack.☆119Updated 2 years ago
- An FPGA accelerator for general-purpose Sparse-Matrix Dense-Matrix Multiplication (SpMM).☆91Updated last year
- A scheduler for spatial DNN accelerators that generate high-performance schedules in one shot using mixed integer programming (MIP)☆83Updated 2 years ago
- Implementations of Buffets, which are efficient, composable idioms for implementing Explicit Decoupled Data Orchestration.☆79Updated 6 years ago
- gem5 repository to study chiplet-based systems☆84Updated 6 years ago
- Benchmarks for Accelerator Design and Customized Architectures☆135Updated 5 years ago