Alternatives and similar repositories for morpher

Users that are interested in morpher are comparing it to the libraries listed below

• ecolab-nus / morpher-v2
  An Open-Source Tool for CGRA Accelerators
  ☆23Updated last year
• pnnl / soda-opt
  ☆46Updated last week
• pku-dasys / pillars
  An integrated CGRA design framework
  ☆90Updated 3 months ago
• tancheng / CGRA-Flow
  CGRA-Flow is an integrated framework for CGRA compilation, exploration, synthesis, and development.
  ☆133Updated 3 weeks ago
• UIUC-ChenLab / ScaleHLS-HIDA
  ☆56Updated 3 months ago
• tancheng / mlir-cgra
  An MLIR dialect to enable the efficient acceleration of ML model on CGRAs.
  ☆59Updated 9 months ago
• pnnl / OpenCGRA
  OpenCGRA is an open-source framework for modeling, testing, and evaluating CGRAs.
  ☆154Updated 2 years ago
• rapidstream-org / rapidstream-tapa
  RapidStream TAPA compiles task-parallel HLS program into high-frequency FPGA accelerators.
  ☆173Updated this week
• tancheng / CGRA-Mapper
  An LLVM pass that can generate CDFG and map the target loops onto a parameterizable CGRA.
  ☆73Updated this week
• zhaijw18 / mcpat-calib-public
  A RISC-V BOOM Microarchitecture Power Modeling Framework
  ☆26Updated 2 years ago
• baichen318 / boom-explorer-public
  The open-sourced version of BOOM-Explorer
  ☆42Updated 2 years ago
• hngenc / stellar
  ☆30Updated 8 months ago
• esl-epfl / OpenEdgeCGRA
  An Open-Hardware CGRA for accelerated computation on the edge.
  ☆30Updated 10 months ago
• KULeuven-MICAS / stream
  Multi-core HW accelerator mapping optimization framework for layer-fused ML workloads.
  ☆54Updated last week
• cornell-zhang / HiSparse
  High-Performance Sparse Linear Algebra on HBM-Equipped FPGAs Using HLS
  ☆93Updated 9 months ago
• arc-research-lab / CHARM
  CHARM: Composing Heterogeneous Accelerators on Heterogeneous SoC Architecture
  ☆147Updated this week
• FCAS-LAB / chiplet_simulators
  A list of our chiplet simulaters
  ☆33Updated 3 weeks ago
• yhqiu16 / TRAM
  Template-based Reconfigurable Architecture Modeling Framework
  ☆14Updated 2 years ago
• cwfletcher / buffets
  Implementations of Buffets, which are efficient, composable idioms for implementing Explicit Decoupled Data Orchestration.
  ☆75Updated 6 years ago
• maeri-project / FEATHER
  A Reconfigurable Accelerator with Data Reordering Support for Low-Cost On-Chip Dataflow Switching
  ☆54Updated 3 months ago
• diwu1990 / uSystolic-Sim
  A systolic array simulator for multi-cycle MACs and varying-byte words, with the paper accepted to HPCA 2022.
  ☆79Updated 3 years ago
• PrincetonUniversity / muchiSim
  Simulator framework for analysis of performance, energy consumption, area and cost of multi-node multi-chiplet tile-based manycore design…
  ☆68Updated last year
• georgia-tech-synergy-lab / SIGMA
  RTL implementation of Flex-DPE.
  ☆106Updated 5 years ago
• GT-CHIPS / gem5_chips
  gem5 repository to study chiplet-based systems
  ☆76Updated 6 years ago
• actlab-genesys / GeneSys
  An open-source parameterizable NPU generator with full-stack multi-target compilation stack for intelligent workloads.
  ☆60Updated 4 months ago
• spcl / rapidchiplet
  A toolchain for rapid design space exploration of chiplet architectures
  ☆53Updated 2 months ago
• esl-epfl / HEEPsilon
  A low power platform based on X-HEEP and integrating the ESL-CGRA
  ☆13Updated 9 months ago
• breagen / MachSuite
  Benchmarks for Accelerator Design and Customized Architectures
  ☆125Updated 5 years ago
• ucb-bar / cosa
  A scheduler for spatial DNN accelerators that generate high-performance schedules in one shot using mixed integer programming (MIP)
  ☆82Updated last year
• MPSLab-ASU / ccf
  CGRA Compilation Framework
  ☆85Updated 2 years ago