A low power platform based on X-HEEP and integrating the ESL-CGRA
☆22Nov 12, 2025Updated 10 months ago
Alternatives and similar repositories for HEEPsilon
Users that are interested in HEEPsilon are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- ESL-CGRA-simulator☆25Apr 10, 2026Updated 5 months ago
- An Open-Hardware CGRA for accelerated computation on the edge.☆56Oct 31, 2025Updated 10 months ago
- Dynamically Reconfigurable Architecture Template and Cycle-level Microarchitecture Simulator for Dataflow AcCelerators☆30Jul 17, 2023Updated 3 years ago
- C++ 17 Hardware abstraction layer generator from systemrdl☆16Aug 28, 2026Updated 3 weeks ago
- eXtensible Heterogeneous Energy-Efficient Platform based on RISC-V☆302Updated this week
- Deploy on Railway without the complexity - Free Credits Offer • AdConnect your repo and Railway handles the rest with instant previews. Quickly provision container image services, databases, and storage volumes.
- An Open-Source Tool for CGRA Accelerators☆34Sep 12, 2025Updated last year
- CGRA Compilation Framework☆93Jul 15, 2023Updated 3 years ago
- ☆17Apr 23, 2026Updated 4 months ago
- An Open-Source Tool for CGRA Accelerators☆91Mar 30, 2026Updated 5 months ago
- Template-based Reconfigurable Architecture Modeling Framework☆14Aug 16, 2022Updated 4 years ago
- matrix-coprocessor for RISC-V☆39Feb 27, 2026Updated 6 months ago
- An LLVM pass that can generate CDFG and map the target loops onto a parameterizable CGRA.☆83Jan 6, 2026Updated 8 months ago
- ☆15Jul 10, 2024Updated 2 years ago
- A high-level performance analysis tool for FPGA-based accelerators☆19Jun 2, 2017Updated 9 years ago
- Wordpress hosting with auto-scaling - Free Trial Offer • AdFully Managed hosting for WordPress and WooCommerce businesses that need reliable, auto-scalable performance. Cloudways SafeUpdates now available.
- An Open-Source Processor for Accelerating Spiking Neural Network☆14Sep 30, 2022Updated 3 years ago
- Used FPGA board and System Verilog to design controller, DMA, pipelined SIMD processor, and GEMM accelerator☆13Aug 26, 2023Updated 3 years ago
- MessagePack implementation for VHDL☆11Nov 29, 2017Updated 8 years ago
- BlueDBM hw/sw implementation using the bluespecpcie PCIe library☆12Dec 25, 2022Updated 3 years ago
- ☆11Jun 28, 2020Updated 6 years ago
- CMake based hardware build system☆45Aug 31, 2026Updated 3 weeks ago
- ☆64Mar 24, 2025Updated last year
- BYU Pynq PR Video Pipeline Hardware☆12Oct 2, 2025Updated 11 months ago
- CGRA framework with vectorization support.☆53Updated this week
- End-to-end encrypted email - Proton Mail • AdSpecial offer: 40% Off Yearly / 80% Off First Month. All Proton services are open source and independently audited for security.
- Ready-to-link, packaged Aurora IP on four QSFP28 lanes, providing 100Gb/s throughput, flow control and status monitoring☆19Sep 7, 2026Updated 2 weeks ago
- A port of the DesignStart Cortex-M0 system to the Diligentinc Arty board☆13Sep 7, 2018Updated 8 years ago
- EQueue Dialect☆43Feb 3, 2022Updated 4 years ago
- [TECS'23] A project on the co-design of Accelerators and CNNs.☆22Dec 10, 2022Updated 3 years ago
- Next generation CGRA generator☆119Aug 26, 2026Updated 3 weeks ago
- MLSys 2021 paper: MicroRec: efficient recommendation inference by hardware and data structure solutions☆21May 26, 2021Updated 5 years ago
- Fork of gem5 with support for manycore architectures. Includes models and scripts to evaluate a software-defined-vector architecture.☆13Oct 14, 2021Updated 4 years ago
- An open source generator for standard cell based memories.☆14Sep 6, 2016Updated 10 years ago
- ☆13Aug 5, 2023Updated 3 years ago
- AI Agents on DigitalOcean Gradient AI Platform • AdBuild production-ready AI agents using customizable tools or access multiple LLMs through a single endpoint. Create custom knowledge bases or connect external data.
- TeLLMe: An Efficient End-to-End Ternary LLM Prefill and Decode Accelerator with Table-Lookup Matmul on Edge FPGAs [FPGA2026]☆38Mar 11, 2026Updated 6 months ago
- Unlimited Vector Extension with Data Streaming Support☆12Nov 25, 2024Updated last year
- 📥 🎯 (1,4/4) an MLIR-based toolchain with Vitis HLS LLVM input/output targeting FPGAs.☆16Nov 15, 2022Updated 3 years ago
- ☆37Updated this week
- DNN Compiler for Heterogeneous SoCs☆76Aug 20, 2026Updated last month
- Generates a SystemVerilog assertion interface for a given SV RTL design☆20Mar 23, 2025Updated last year
- Old version of the desktop client for the WebIssues team collaboration system.☆13May 14, 2020Updated 6 years ago