A low power platform based on X-HEEP and integrating the ESL-CGRA
☆18Nov 12, 2025Updated 5 months ago
Alternatives and similar repositories for HEEPsilon
Users that are interested in HEEPsilon are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- HierCGRA: An Open-Source Framework for Large-Scale CGRA with Hierarchical Modeling and Automated Exploration☆14Mar 6, 2023Updated 3 years ago
- An Open-Hardware CGRA for accelerated computation on the edge.☆51Oct 31, 2025Updated 6 months ago
- C++ 17 Hardware abstraction layer generator from systemrdl☆15Apr 12, 2026Updated 3 weeks ago
- eXtensible Heterogeneous Energy-Efficient Platform based on RISC-V☆262Apr 24, 2026Updated last week
- ESL-CGRA-simulator☆20Apr 10, 2026Updated 3 weeks ago
- GPU virtual machines on DigitalOcean Gradient AI • AdGet to production fast with high-performance AMD and NVIDIA GPUs you can spin up in seconds. The definition of operational simplicity.
- OpenMP front-end based on LLVM for CGRAs☆10Oct 2, 2022Updated 3 years ago
- Dynamically Reconfigurable Architecture Template and Cycle-level Microarchitecture Simulator for Dataflow AcCelerators☆29Jul 17, 2023Updated 2 years ago
- matrix-coprocessor for RISC-V☆32Feb 27, 2026Updated 2 months ago
- An LLVM pass that can generate CDFG and map the target loops onto a parameterizable CGRA.☆80Jan 6, 2026Updated 3 months ago
- Template-based Reconfigurable Architecture Modeling Framework☆14Aug 16, 2022Updated 3 years ago
- An Open-Source Tool for CGRA Accelerators☆32Sep 12, 2025Updated 7 months ago
- CGRA Compilation Framework☆92Jul 15, 2023Updated 2 years ago
- An Open-Source Processor for Accelerating Spiking Neural Network☆12Sep 30, 2022Updated 3 years ago
- A high-level performance analysis tool for FPGA-based accelerators☆19Jun 2, 2017Updated 8 years ago
- Deploy open-source AI quickly and easily - Special Bonus Offer • AdRunpod Hub is built for open source. One-click deployment and autoscaling endpoints without provisioning your own infrastructure.
- BYU Pynq PR Video Pipeline Hardware☆13Oct 2, 2025Updated 7 months ago
- ☆11Jun 28, 2020Updated 5 years ago
- MessagePack implementation for VHDL☆11Nov 29, 2017Updated 8 years ago
- BlueDBM hw/sw implementation using the bluespecpcie PCIe library☆12Dec 25, 2022Updated 3 years ago
- ☆62Mar 24, 2025Updated last year
- An Open-Source Tool for CGRA Accelerators☆83Mar 30, 2026Updated last month
- A stream to RTL compiler based on MLIR and CIRCT☆16Nov 15, 2022Updated 3 years ago
- CORE-V eXtension Interface compliant RISC-V [F|Zfinx] Coprocessor☆15Nov 12, 2025Updated 5 months ago
- CMake based hardware build system☆38Apr 24, 2026Updated last week
- AI Agents on DigitalOcean Gradient AI Platform • AdBuild production-ready AI agents using customizable tools or access multiple LLMs through a single endpoint. Create custom knowledge bases or connect external data.
- EQueue Dialect☆42Feb 3, 2022Updated 4 years ago
- [TECS'23] A project on the co-design of Accelerators and CNNs.☆21Dec 10, 2022Updated 3 years ago
- Next generation CGRA generator☆120Updated this week
- 📥 🎯 (1,4/4) an MLIR-based toolchain with Vitis HLS LLVM input/output targeting FPGAs.☆15Nov 15, 2022Updated 3 years ago
- A Plug-and-play Lightweight tool for the Inference Optimization of Deep Neural networks☆50Apr 16, 2026Updated 2 weeks ago
- Fork of gem5 with support for manycore architectures. Includes models and scripts to evaluate a software-defined-vector architecture.☆12Oct 14, 2021Updated 4 years ago
- MLSys 2021 paper: MicroRec: efficient recommendation inference by hardware and data structure solutions☆19May 26, 2021Updated 4 years ago
- RangeSanitizer (RSan) detects spatial and temporal memory errors in C/C++ programs using efficient range checks.☆19Nov 4, 2025Updated 5 months ago
- An open source generator for standard cell based memories.☆14Sep 6, 2016Updated 9 years ago
- Deploy to Railway using AI coding agents - Free Credits Offer • AdUse Claude Code, Codex, OpenCode, and more. Autonomous software development now has the infrastructure to match with Railway.
- Unlimited Vector Extension with Data Streaming Support☆12Nov 25, 2024Updated last year
- A bit-level sparsity-awared multiply-accumulate process element.☆19Jul 9, 2024Updated last year
- Heterogeneous simulator for DECADES Project☆32May 23, 2024Updated last year
- ☆12Aug 5, 2023Updated 2 years ago
- ☆26Jan 30, 2026Updated 3 months ago
- ☆63Feb 18, 2019Updated 7 years ago
- LEN5 is a configurable, speculative, out-of-order, 64-bit RISC-V microprocessor targetting etherogeneus systems on chip.☆21Oct 22, 2025Updated 6 months ago