esl-epfl / HEEPsilonLinks
A low power platform based on X-HEEP and integrating the ESL-CGRA
☆13Updated 9 months ago
Alternatives and similar repositories for HEEPsilon
Users that are interested in HEEPsilon are comparing it to the libraries listed below
Sorting:
- An Open-Source Tool for CGRA Accelerators☆67Updated 2 months ago
- Template-based Reconfigurable Architecture Modeling Framework☆14Updated 2 years ago
- An integrated CGRA design framework☆90Updated 3 months ago
- An Open-Hardware CGRA for accelerated computation on the edge.☆30Updated 10 months ago
- CGRA-Flow is an integrated framework for CGRA compilation, exploration, synthesis, and development.☆133Updated 3 weeks ago
- ☆17Updated 2 months ago
- An Open-Source Tool for CGRA Accelerators☆23Updated last year
- ☆43Updated 10 months ago
- ☆46Updated last week
- A systolic array simulator for multi-cycle MACs and varying-byte words, with the paper accepted to HPCA 2022.☆79Updated 3 years ago
- eyeriss-chisel3☆41Updated 3 years ago
- A list of our chiplet simulaters☆33Updated 3 weeks ago
- A RISC-V BOOM Microarchitecture Power Modeling Framework☆26Updated 2 years ago
- OpenCGRA is an open-source framework for modeling, testing, and evaluating CGRAs.☆154Updated 2 years ago
- RapidStream TAPA compiles task-parallel HLS program into high-frequency FPGA accelerators.☆173Updated this week
- INT8 & FP16 multiplier accumulator (MAC) design with UVM verification completed.☆103Updated 4 years ago
- ☆60Updated 2 months ago
- A Reconfigurable Accelerator with Data Reordering Support for Low-Cost On-Chip Dataflow Switching☆54Updated 3 months ago
- The RAD flow is an open-source academic architecture exploration and evaluation flow for novel beyond-FPGA reconfigurable acceleration de…☆38Updated last month
- A SystemVerilog implementation of Row-Stationary dataflow and Hierarchical Mesh Network-on-Chip Architecture based on Eyeriss CNN Acceler…☆163Updated 5 years ago
- A toolchain for rapid design space exploration of chiplet architectures☆53Updated 2 months ago
- NoC (Network-on-Chip) generator that generates Verilog HDL model of NoC consisting of on-chip routers☆65Updated 5 years ago
- Verilog implementation of Softmax function☆67Updated 2 years ago
- ☆30Updated last month
- [FPGA 2021, Best Paper Award] An automated floorplanning and pipelining tool for Vivado HLS.☆122Updated 2 years ago
- 16-bit Adder Multiplier hardware on Digilent Basys 3☆76Updated last year
- A verilog implementation for Network-on-Chip☆74Updated 7 years ago
- Deep Learning Accelerator Based on Eyeriss V2 Architecture with custom RISC-V extended instructions☆197Updated 5 years ago
- An FPGA accelerator for general-purpose Sparse-Matrix Dense-Matrix Multiplication (SpMM).☆80Updated 11 months ago
- Public release☆53Updated 5 years ago