esl-epfl / HEEPsilonLinks
A low power platform based on X-HEEP and integrating the ESL-CGRA
☆14Updated 7 months ago
Alternatives and similar repositories for HEEPsilon
Users that are interested in HEEPsilon are comparing it to the libraries listed below
Sorting:
- An Open-Source Tool for CGRA Accelerators☆21Updated last year
- Template-based Reconfigurable Architecture Modeling Framework☆14Updated 2 years ago
- An Open-Source Tool for CGRA Accelerators☆65Updated last month
- An Open-Hardware CGRA for accelerated computation on the edge.☆26Updated 8 months ago
- ☆44Updated this week
- An integrated CGRA design framework☆88Updated 2 months ago
- A systolic array simulator for multi-cycle MACs and varying-byte words, with the paper accepted to HPCA 2022.☆77Updated 3 years ago
- ☆15Updated 2 years ago
- ☆16Updated 3 weeks ago
- A list of our chiplet simulaters☆32Updated 2 months ago
- Ratatoskr NoC Simulator☆26Updated 4 years ago
- eyeriss-chisel3☆40Updated 3 years ago
- An LLVM pass that can generate CDFG and map the target loops onto a parameterizable CGRA.☆72Updated 3 weeks ago
- CGRA-Flow is an integrated framework for CGRA compilation, exploration, synthesis, and development.☆129Updated last week
- CGRA framework with vectorization support.☆30Updated 3 weeks ago
- DRA+RISC-V Exploration Framework☆16Updated last year
- An example of using Ramulator as memory model in a cycle-accurate SystemC Design☆50Updated 7 years ago
- NoC (Network-on-Chip) generator that generates Verilog HDL model of NoC consisting of on-chip routers☆63Updated 5 years ago
- The RAD flow is an open-source academic architecture exploration and evaluation flow for novel beyond-FPGA reconfigurable acceleration de…☆36Updated 2 weeks ago
- A RISC-V BOOM Microarchitecture Power Modeling Framework☆24Updated 2 years ago
- [DATE 2022] PowerGear: Early-Stage Power Estimation in FPGA HLS via Heterogeneous Edge-Centric GNNs☆17Updated 3 years ago
- ☆20Updated 2 years ago
- ☆33Updated 6 years ago
- ☆29Updated 6 months ago
- An MLIR dialect to enable the efficient acceleration of ML model on CGRAs.☆59Updated 7 months ago
- Project repo for the POSH on-chip network generator☆46Updated 2 months ago
- SAURIA (Systolic-Array tensor Unit for aRtificial Intelligence Acceleration) is an open-source Convolutional Neural Network accelerator b…☆43Updated 8 months ago
- CORE-V eXtension Interface compliant RISC-V [F|Zfinx] Coprocessor☆11Updated 7 months ago
- ☆53Updated 2 months ago
- A Reconfigurable Accelerator with Data Reordering Support for Low-Cost On-Chip Dataflow Switching☆53Updated 2 months ago