cornell-brg / pymtl3-net
Project repo for the POSH on-chip network generator
☆44Updated this week
Alternatives and similar repositories for pymtl3-net:
Users that are interested in pymtl3-net are comparing it to the libraries listed below
- An example of using Ramulator as memory model in a cycle-accurate SystemC Design☆48Updated 7 years ago
- A 32-bit RISC-V Processor Designed with High-Level Synthesis☆52Updated 5 years ago
- HLS for Networks-on-Chip☆33Updated 4 years ago
- CGRA framework with vectorization support.☆27Updated this week
- ☆26Updated 5 years ago
- Prototype-network-on-chip (ProNoC) is an EDA tool that facilitates prototyping of custom heterogeneous NoC-based many-core-SoC (MCSoC).☆52Updated last week
- Tests for example Rocket Custom Coprocessors☆73Updated 5 years ago
- Development of a Network on Chip Simulation using SystemC.☆31Updated 7 years ago
- Ratatoskr NoC Simulator☆24Updated 3 years ago
- Digital Hardware Modelling using VHDL, Verilog, SystemVerilog, SystemC, HLS(C++, OpenCL)☆63Updated last month
- Contains FPGA benchmarks for Vivado HLS and Catapult HLS☆26Updated 4 years ago
- ☆87Updated last year
- CGRA-Flow is an integrated framework for CGRA compilation, exploration, synthesis, and development.☆121Updated last week
- CHIPKIT: An agile, reusable open-source framework for rapid test chip development☆41Updated 4 years ago
- contains TLM2 based interfaces for AXI, ACE, CHI and other standard protocols☆56Updated last month
- ☆71Updated 10 years ago
- NoC (Network-on-Chip) generator that generates Verilog HDL model of NoC consisting of on-chip routers☆60Updated 5 years ago
- An LLVM pass that can generate CDFG and map the target loops onto a parameterizable CGRA.☆64Updated last week
- An integrated CGRA design framework☆87Updated this week
- A Style Guide for the Chisel Hardware Construction Language☆107Updated 3 years ago
- ☆53Updated 4 years ago
- Modular Multi-ported SRAM-based Memory☆29Updated 4 months ago
- SystemVerilog modules and classes commonly used for verification☆46Updated 2 months ago
- Public release☆50Updated 5 years ago
- AutoSVA is a tool to automatically generate formal testbenches for unit-level RTL verification. The goal is to, based on annotations made…☆76Updated 11 months ago
- General Purpose AXI Direct Memory Access☆49Updated 10 months ago
- Source code of the paper "Low-Cost and Programmable CRC Implementation based on FPGA"☆42Updated 4 years ago
- RTL sources of the High-Performance L1 Dcache (HPDcache) for OpenHW CV cores☆68Updated last week
- A High-Level DRAM Timing, Power and Area Exploration Tool☆28Updated 4 years ago
- Matchlib Connections Library - latency insensitive channels (from NVlabs/matchlib/connections)☆37Updated 6 months ago