cornell-brg / pymtl3-netView external linksLinks
Project repo for the POSH on-chip network generator
☆52Mar 18, 2025Updated 10 months ago
Alternatives and similar repositories for pymtl3-net
Users that are interested in pymtl3-net are comparing it to the libraries listed below
Sorting:
- The programming runtime and interfaces for ARENA.☆14Sep 14, 2021Updated 4 years ago
- PyMTL3 wrapper of the Berkeley Hardfloat IP☆10Aug 9, 2023Updated 2 years ago
- OpenCGRA is an open-source framework for modeling, testing, and evaluating CGRAs.☆167Mar 2, 2023Updated 2 years ago
- An LLVM pass that can generate CDFG and map the target loops onto a parameterizable CGRA.☆79Jan 6, 2026Updated last month
- ☆33Nov 6, 2024Updated last year
- CGRA-Flow is an integrated framework for CGRA compilation, exploration, synthesis, and development.☆152Feb 6, 2026Updated last week
- An MLIR dialect to enable the efficient acceleration of ML model on CGRAs.☆65Oct 9, 2024Updated last year
- Code for PyMTL Tutorial @ ISCA 2019☆11Jun 22, 2019Updated 6 years ago
- Pymtl 3 (Mamba), an open-source Python-based hardware generation, simulation, and verification framework☆445Aug 24, 2025Updated 5 months ago
- Next generation CGRA generator☆118Feb 4, 2026Updated last week
- An Open-Source Silicon Compiler for Reduced-Complexity Reconfigurable Fabrics☆14Updated this week
- CGRA framework with vectorization support.☆43Jan 29, 2026Updated 2 weeks ago
- Dynamically Reconfigurable Architecture Template and Cycle-level Microarchitecture Simulator for Dataflow AcCelerators☆30Jul 17, 2023Updated 2 years ago
- Template-based Reconfigurable Architecture Modeling Framework☆14Aug 16, 2022Updated 3 years ago
- An HBM FPGA based SpMV Accelerator☆17Aug 29, 2024Updated last year
- ☆14Feb 1, 2026Updated 2 weeks ago
- Industry standard I/O for nMigen☆12Apr 23, 2020Updated 5 years ago
- ☆18Feb 3, 2022Updated 4 years ago
- Systolic Three Matrix Multiplier for Graph Convolutional Networks using High Level Synthesis☆23Jul 29, 2022Updated 3 years ago
- FPU Generator☆20Jul 19, 2021Updated 4 years ago
- tools regarding on analog modeling, validation, and generation☆22Apr 11, 2023Updated 2 years ago
- This repository contains iCEBreaker examples for Amaranth HDL.☆39Oct 31, 2023Updated 2 years ago
- MICRO 2023 Evaluation Artifact for TeAAL☆10Oct 26, 2023Updated 2 years ago
- CGRA Compilation Framework☆91Jul 15, 2023Updated 2 years ago
- BookSim 2.0☆399Jun 24, 2024Updated last year
- Python-based hardware modeling framework☆245Oct 27, 2019Updated 6 years ago
- Network on Chip for MPSoC☆28Jan 27, 2026Updated 2 weeks ago
- An Open-Source Tool for CGRA Accelerators☆30Sep 12, 2025Updated 5 months ago
- A portable framework to map DFG (dataflow graph, representing an application) on spatial accelerators.☆40Oct 31, 2022Updated 3 years ago
- ☆10Apr 8, 2021Updated 4 years ago
- RISC-V 32-bit core for MCCI Catena 4710☆10Jul 31, 2019Updated 6 years ago
- A home for Genesis2 sources.☆44Jul 9, 2025Updated 7 months ago
- Business Rule Engine Hardware Accelerator☆14Jun 18, 2020Updated 5 years ago
- MAERI: A DNN accelerator with reconfigurable interconnects to support flexible dataflow (http://synergy.ece.gatech.edu/tools/maeri/)☆67Sep 24, 2021Updated 4 years ago
- ☆71Mar 22, 2020Updated 5 years ago
- Verilog FPGA Parts Library. Old Octavo soft-CPU project.☆76Apr 2, 2019Updated 6 years ago
- Four versions of MIPS 32bit implemented in Verilog using Vivado, ready for Simulation and Nexys4 DDR Board☆12Sep 15, 2022Updated 3 years ago
- Approximate arithmetic circuits for FPGAs☆13Feb 19, 2020Updated 5 years ago
- Verilog Examples and WebFPGA Standard Library☆11Nov 25, 2019Updated 6 years ago