EQueue Dialect
☆42Feb 3, 2022Updated 4 years ago
Alternatives and similar repositories for EventQueue
Users that are interested in EventQueue are comparing it to the libraries listed below
Sorting:
- Release of stream-specialization software/hardware stack.☆120May 5, 2023Updated 2 years ago
- OpenMP front-end based on LLVM for CGRAs☆10Oct 2, 2022Updated 3 years ago
- Bridging polyhedral analysis tools to the MLIR framework☆119Sep 9, 2023Updated 2 years ago
- ☆62Mar 24, 2025Updated 11 months ago
- CGRA-Flow is an integrated framework for CGRA compilation, exploration, synthesis, and development.☆155Feb 18, 2026Updated last month
- ☆26Oct 6, 2023Updated 2 years ago
- A high-level performance analysis tool for FPGA-based accelerators☆19Jun 2, 2017Updated 8 years ago
- Differentiable Combinatorial Scheduling at Scale (ICML'24). Mingju Liu, Yingjie Li, Jiaqi Yin, Zhiru Zhang, Cunxi Yu.☆22Oct 31, 2024Updated last year
- The Next-gen Language & Compiler Powering Efficient Hardware Design☆36Jan 16, 2025Updated last year
- ☆17Mar 26, 2025Updated 11 months ago
- A novel spatial accelerator for horizontal diffusion weather stencil computation, as described in ICS 2023 paper by Singh et al. (https:/…☆22Jul 27, 2023Updated 2 years ago
- CGRA Compilation Framework☆91Jul 15, 2023Updated 2 years ago
- Artifact of ASPLOS'23 paper entitled: GRACE: A Scalable Graph-Based Approach to Accelerating Recommendation Model Inference☆19Mar 5, 2023Updated 3 years ago
- Domain-Specific Architecture Generator 2☆22Oct 2, 2022Updated 3 years ago
- Fast PnR toolchain for CGRA☆18Jul 26, 2024Updated last year
- AIM: Accelerating Arbitrary-precision Integer Multiplication on Heterogeneous Reconfigurable Computing Platform Versal ACAP (Full Paper a…☆26May 18, 2025Updated 10 months ago
- HeteroHalide: From Image Processing DSL to Efficient FPGA Acceleration☆15Sep 14, 2020Updated 5 years ago
- A scalable High-Level Synthesis framework on MLIR☆291May 15, 2024Updated last year
- An MLIR dialect to enable the efficient acceleration of ML model on CGRAs.☆65Oct 9, 2024Updated last year
- ☆15Jun 14, 2022Updated 3 years ago
- Sharing the codebase and steps for artifact evaluation for ISCA 2023 paper☆15Feb 20, 2024Updated 2 years ago
- ☆12Jul 9, 2021Updated 4 years ago
- PyTorch compilation tutorial covering TorchScript, torch.fx, and Slapo☆17Mar 13, 2023Updated 3 years ago
- MessagePack implementation for VHDL☆11Nov 29, 2017Updated 8 years ago
- BlueDBM hw/sw implementation using the bluespecpcie PCIe library☆12Dec 25, 2022Updated 3 years ago
- ☆31Feb 22, 2024Updated 2 years ago
- FPGA synthesis tool powered by program synthesis☆55Dec 15, 2025Updated 3 months ago
- HeteroCL-MLIR dialect for accelerator design☆42Sep 18, 2024Updated last year
- Fork of gem5 with support for manycore architectures. Includes models and scripts to evaluate a software-defined-vector architecture.☆12Oct 14, 2021Updated 4 years ago
- Data-Centric MLIR dialect☆46Oct 16, 2023Updated 2 years ago
- ☆17Oct 17, 2025Updated 5 months ago
- Fast, Accurate and Convenient Light-Weight HLS Framework for Academic Design Space Exploration and Evaluation. (LLVM-11)☆62Mar 17, 2022Updated 4 years ago
- The code for our paper "Neural Architecture Search as Program Transformation Exploration"☆16Apr 28, 2021Updated 4 years ago
- ☆33Dec 1, 2022Updated 3 years ago
- FACE: Fast and Customizable Sorting Accelerator☆11Sep 6, 2016Updated 9 years ago
- Generator for MLIR files from known front-ends☆16Oct 31, 2023Updated 2 years ago
- CHARM: Composing Heterogeneous Accelerators on Heterogeneous SoC Architecture☆168Mar 12, 2026Updated last week
- A Comprehensive Model-Based Analysis Framework for High Level Synthesis of Real Applications☆38Oct 20, 2020Updated 5 years ago
- MICRO 2023 Evaluation Artifact for TeAAL☆10Oct 26, 2023Updated 2 years ago