harvard-acc / gem5-aladdinLinks
End-to-end SoC simulation: integrating the gem5 system simulator with the Aladdin accelerator simulator.
☆237Updated 2 years ago
Alternatives and similar repositories for gem5-aladdin
Users that are interested in gem5-aladdin are comparing it to the libraries listed below
Sorting:
- A pre-RTL, power-performance model for fixed-function accelerators☆177Updated last year
- An integrated power, area, and timing modeling framework for multicore and manycore architectures☆187Updated 4 years ago
- Fast and accurate DRAM power and energy estimation tool☆165Updated last week
- DRAMsim3: a Cycle-accurate, Thermal-Capable DRAM Simulator☆378Updated 10 months ago
- DRAMSim2: A cycle accurate DRAM simulator☆273Updated 4 years ago
- CGRA-Flow is an integrated framework for CGRA compilation, exploration, synthesis, and development.☆132Updated last week
- SMAUG: Simulating Machine Learning Applications Using Gem5-Aladdin☆109Updated 2 years ago
- Benchmarks for Accelerator Design and Customized Architectures☆124Updated 5 years ago
- ☆91Updated last year
- DRAMSys a SystemC TLM-2.0 based DRAM simulator.☆280Updated last month
- AutoSA: Polyhedral-Based Systolic Array Compiler☆221Updated 2 years ago
- Implementations of Buffets, which are efficient, composable idioms for implementing Explicit Decoupled Data Orchestration.☆72Updated 6 years ago
- Release of stream-specialization software/hardware stack.☆122Updated 2 years ago
- OpenCGRA is an open-source framework for modeling, testing, and evaluating CGRAs.☆153Updated 2 years ago
- BookSim 2.0☆341Updated last year
- SystemC/C++ library of commonly-used hardware functions and components for HLS.☆274Updated 2 months ago
- Official repository of the Arm Research Starter Kit on System Modeling using gem5☆115Updated last week
- Rosetta: A Realistic High-level Synthesis Benchmark Suite for Software Programmable FPGAs☆165Updated last year
- CGRA Compilation Framework☆84Updated last year
- Repository to host and maintain scale-sim-v2 code☆302Updated 2 months ago
- An integrated cache and memory access time, cycle time, area, leakage, and dynamic power model☆468Updated 11 months ago
- RiVEC Bencmark Suite☆117Updated 6 months ago
- Deep Learning Accelerator Based on Eyeriss V2 Architecture with custom RISC-V extended instructions☆195Updated 5 years ago
- Ramulator 2.0 is a modern, modular, extensible, and fast cycle-accurate DRAM simulator. It provides support for agile implementation and …☆352Updated last month
- A scalable High-Level Synthesis framework on MLIR☆261Updated last year
- NVSim - A performance, energy and area estimation tool for non-volatile memory (NVM)☆115Updated 6 years ago
- A fast and flexible simulation infrastructure for exploring general-purpose processing-in-memory (PIM) architectures. Ramulator-PIM combi…☆170Updated 2 years ago
- RapidStream TAPA compiles task-parallel HLS program into high-frequency FPGA accelerators.☆172Updated this week
- A Chisel RTL generator for network-on-chip interconnects☆202Updated last month
- gem5 repository to study chiplet-based systems☆75Updated 6 years ago