pku-dasys / pillarsLinks
An integrated CGRA design framework
☆90Updated 4 months ago
Alternatives and similar repositories for pillars
Users that are interested in pillars are comparing it to the libraries listed below
Sorting:
- CGRA-Flow is an integrated framework for CGRA compilation, exploration, synthesis, and development.☆135Updated last month
- An Open-Source Tool for CGRA Accelerators☆67Updated 3 months ago
- An Open-Source Tool for CGRA Accelerators☆23Updated last year
- OpenCGRA is an open-source framework for modeling, testing, and evaluating CGRAs.☆155Updated 2 years ago
- ☆47Updated last month
- Template-based Reconfigurable Architecture Modeling Framework☆14Updated 2 years ago
- RapidStream TAPA compiles task-parallel HLS program into high-frequency FPGA accelerators.☆173Updated this week
- The open-sourced version of BOOM-Explorer☆43Updated 2 years ago
- A RISC-V BOOM Microarchitecture Power Modeling Framework☆27Updated 2 years ago
- An MLIR dialect to enable the efficient acceleration of ML model on CGRAs.☆60Updated 10 months ago
- A list of our chiplet simulaters☆33Updated last month
- CGRA Compilation Framework☆84Updated 2 years ago
- A systolic array simulator for multi-cycle MACs and varying-byte words, with the paper accepted to HPCA 2022.☆80Updated 3 years ago
- An LLVM pass that can generate CDFG and map the target loops onto a parameterizable CGRA.☆74Updated 2 weeks ago
- ☆56Updated 4 months ago
- [FPGA 2021, Best Paper Award] An automated floorplanning and pipelining tool for Vivado HLS.☆122Updated 2 years ago
- High-Performance Sparse Linear Algebra on HBM-Equipped FPGAs Using HLS☆94Updated 10 months ago
- gem5 repository to study chiplet-based systems☆78Updated 6 years ago
- ☆15Updated 3 years ago
- MAERI: A DNN accelerator with reconfigurable interconnects to support flexible dataflow (http://synergy.ece.gatech.edu/tools/maeri/)☆64Updated 3 years ago
- An FPGA accelerator for general-purpose Sparse-Matrix Dense-Matrix Multiplication (SpMM).☆81Updated last year
- Benchmarks for Accelerator Design and Customized Architectures☆128Updated 5 years ago
- A low power platform based on X-HEEP and integrating the ESL-CGRA☆13Updated 10 months ago
- The RAD flow is an open-source academic architecture exploration and evaluation flow for novel beyond-FPGA reconfigurable acceleration de…☆38Updated 2 weeks ago
- Tests for example Rocket Custom Coprocessors☆75Updated 5 years ago
- A toolchain for rapid design space exploration of chiplet architectures☆56Updated 2 weeks ago
- ☆60Updated 3 months ago
- ☆87Updated last year
- RTL implementation of Flex-DPE.☆108Updated 5 years ago
- ☆43Updated 10 months ago