pku-dasys / pillarsLinks
An integrated CGRA design framework
☆90Updated 6 months ago
Alternatives and similar repositories for pillars
Users that are interested in pillars are comparing it to the libraries listed below
Sorting:
- CGRA-Flow is an integrated framework for CGRA compilation, exploration, synthesis, and development.☆137Updated 3 months ago
- An Open-Source Tool for CGRA Accelerators☆73Updated last week
- An Open-Source Tool for CGRA Accelerators☆24Updated last week
- A list of our chiplet simulaters☆38Updated 2 months ago
- Template-based Reconfigurable Architecture Modeling Framework☆14Updated 3 years ago
- The open-sourced version of BOOM-Explorer☆43Updated 2 years ago
- TAPA compiles task-parallel HLS program into high-performance FPGA accelerators.☆174Updated last month
- OpenCGRA is an open-source framework for modeling, testing, and evaluating CGRAs.☆160Updated 2 years ago
- ☆49Updated 2 months ago
- ☆58Updated 5 months ago
- A systolic array simulator for multi-cycle MACs and varying-byte words, with the paper accepted to HPCA 2022.☆80Updated 3 years ago
- CGRA Compilation Framework☆87Updated 2 years ago
- [FPGA 2021, Best Paper Award] An automated floorplanning and pipelining tool for Vivado HLS.☆124Updated 2 years ago
- High-Performance Sparse Linear Algebra on HBM-Equipped FPGAs Using HLS☆95Updated 11 months ago
- An MLIR dialect to enable the efficient acceleration of ML model on CGRAs.☆61Updated 11 months ago
- MAERI: A DNN accelerator with reconfigurable interconnects to support flexible dataflow (http://synergy.ece.gatech.edu/tools/maeri/)☆66Updated 3 years ago
- A RISC-V BOOM Microarchitecture Power Modeling Framework☆29Updated 2 years ago
- Dataset for ML-guided Accelerator Design☆38Updated 10 months ago
- eyeriss-chisel3☆41Updated 3 years ago
- gem5 repository to study chiplet-based systems☆81Updated 6 years ago
- Benchmarks for Accelerator Design and Customized Architectures☆129Updated 5 years ago
- MasterRTL: A Pre-Synthesis PPA Estimation Framework for Any RTL Design☆54Updated 3 months ago
- An LLVM pass that can generate CDFG and map the target loops onto a parameterizable CGRA.☆74Updated 3 weeks ago
- A toolchain for rapid design space exploration of chiplet architectures☆59Updated last month
- An example of using Ramulator as memory model in a cycle-accurate SystemC Design☆52Updated 8 years ago
- An MLIR Complier for PyTorch/C/C++ Codes into HLS Dataflow Designs☆47Updated last month
- Implementations of Buffets, which are efficient, composable idioms for implementing Explicit Decoupled Data Orchestration.☆77Updated 6 years ago
- CGRA framework with vectorization support.☆35Updated last week
- ☆44Updated last year
- A Reconfigurable Accelerator with Data Reordering Support for Low-Cost On-Chip Dataflow Switching☆63Updated last month