yhqiu16 / FDRALinks
DRA+RISC-V Exploration Framework
☆18Updated last year
Alternatives and similar repositories for FDRA
Users that are interested in FDRA are comparing it to the libraries listed below
Sorting:
- An Open-Source Tool for CGRA Accelerators☆27Updated 3 months ago
- CGRA-Flow is an integrated framework for CGRA compilation, exploration, synthesis, and development.☆149Updated this week
- A RISC-V BOOM Microarchitecture Power Modeling Framework☆30Updated 2 years ago
- An integrated CGRA design framework☆91Updated 9 months ago
- An Open-Source Tool for CGRA Accelerators☆80Updated 3 months ago
- HW Architecture-Mapping Design Space Exploration Framework for Deep Learning Accelerators☆175Updated 2 months ago
- AutoSA: Polyhedral-Based Systolic Array Compiler☆236Updated 3 years ago
- An MLIR Complier for PyTorch/C/C++ Codes into HLS Dataflow Designs☆56Updated 4 months ago
- Template-based Reconfigurable Architecture Modeling Framework☆14Updated 3 years ago
- TAPA compiles task-parallel HLS program into high-performance FPGA accelerators. UCLA-maintained.☆176Updated 4 months ago
- CHARM: Composing Heterogeneous Accelerators on Heterogeneous SoC Architecture☆162Updated this week
- A reading list for SRAM-based Compute-In-Memory (CIM) research.☆109Updated 2 months ago
- RTL implementation of Flex-DPE.☆115Updated 5 years ago
- A Reconfigurable Accelerator with Data Reordering Support for Low-Cost On-Chip Dataflow Switching☆73Updated 2 months ago
- A list of our chiplet simulaters☆46Updated 6 months ago
- FSA: Fusing FlashAttention within a Single Systolic Array☆81Updated 4 months ago
- An open-source parameterizable NPU generator with full-stack multi-target compilation stack for intelligent workloads.☆69Updated 3 months ago
- ☆46Updated last year
- ☆61Updated 9 months ago
- ☆123Updated 5 years ago
- A SystemVerilog implementation of Row-Stationary dataflow and Hierarchical Mesh Network-on-Chip Architecture based on Eyeriss CNN Acceler…☆177Updated 6 years ago
- 关于移植模型至gemmini的文档☆32Updated 3 years ago
- Multi-core HW accelerator mapping optimization framework for layer-fused ML workloads.☆64Updated 5 months ago
- The framework for the paper "Inter-layer Scheduling Space Definition and Exploration for Tiled Accelerators" in ISCA 2023.☆81Updated 9 months ago
- ☆51Updated last month
- Allo Accelerator Design and Programming Framework☆316Updated last week
- PANDA: Architecture-Level Power Evaluation by Unifying Analytical and Machine Learning Solutions☆17Updated 2 years ago
- ☆21Updated 3 months ago
- verilog实现TPU中的脉动阵列计算卷积的module☆148Updated 7 months ago
- An FPGA accelerator for general-purpose Sparse-Matrix Dense-Matrix Multiplication (SpMM).☆92Updated last year