tancheng / VectorCGRALinks
CGRA framework with vectorization support.
☆35Updated last week
Alternatives and similar repositories for VectorCGRA
Users that are interested in VectorCGRA are comparing it to the libraries listed below
Sorting:
- An MLIR dialect to enable the efficient acceleration of ML model on CGRAs.☆61Updated 11 months ago
- An LLVM pass that can generate CDFG and map the target loops onto a parameterizable CGRA.☆74Updated 3 weeks ago
- CGRA-Flow is an integrated framework for CGRA compilation, exploration, synthesis, and development.☆136Updated 2 months ago
- ☆60Updated last week
- An integrated CGRA design framework☆91Updated 5 months ago
- OpenCGRA is an open-source framework for modeling, testing, and evaluating CGRAs.☆158Updated 2 years ago
- CIRCT-based HLS compilation flows, debugging, and cosimulation tools.☆50Updated 2 years ago
- ☆16Updated 2 years ago
- ☆15Updated 3 years ago
- A fast, accurate trace-based simulator for High-Level Synthesis.☆68Updated 5 months ago
- An Open-Source Tool for CGRA Accelerators☆72Updated last week
- PiDRAM is the first flexible end-to-end framework that enables system integration studies and evaluation of real Processing-using-Memory …☆69Updated last year
- A 32-bit RISC-V Processor Designed with High-Level Synthesis☆54Updated 5 years ago
- ☆87Updated last year
- ☆49Updated 2 months ago
- An Open-Hardware CGRA for accelerated computation on the edge.☆33Updated last year
- A GPU acceleration flow for RTL simulation with batch stimulus☆113Updated last year
- [FPGA 2022, Best Paper Award] Parallel placement and routing of Vivado HLS dataflow designs.☆127Updated 2 years ago
- A toolchain for rapid design space exploration of chiplet architectures☆59Updated last month
- ☆63Updated 4 months ago
- ☆58Updated 5 months ago
- Tests for example Rocket Custom Coprocessors☆75Updated 5 years ago
- Transactional Verilog design and Verilator Testbench for a RISC-V TensorCore Vector co-processor for reproducible linear algebra☆57Updated 3 years ago
- ☆58Updated 2 years ago
- [FPGA 2021, Best Paper Award] An automated floorplanning and pipelining tool for Vivado HLS.☆123Updated 2 years ago
- Next generation CGRA generator☆114Updated this week
- Fork of seldridge/rocket-rocc-examples with tests for a systolic array based matmul accelerator☆60Updated 2 months ago
- DASS HLS Compiler☆29Updated last year
- Implementations of Buffets, which are efficient, composable idioms for implementing Explicit Decoupled Data Orchestration.☆77Updated 6 years ago
- gem5 repository to study chiplet-based systems☆81Updated 6 years ago