PolyArch / stream-dataflow
Public Release of Stream-Dataflow
☆14Updated 5 years ago
Related projects ⓘ
Alternatives and complementary repositories for stream-dataflow
- Polyhedral High-Level Synthesis in MLIR☆29Updated last year
- PARADE: A Cycle-Accurate Full-System Simulation Platform for Accelerator-Rich Architectural Design and Exploration☆46Updated 2 years ago
- Source code of the simulator used in the Mosaic paper from MICRO 2017: "Mosaic: A GPU Memory Manager with Application-Transparent Support…☆40Updated 6 years ago
- Repository for the tools and non-commercial data used for the "Accelerator wall" paper.☆47Updated 5 years ago
- Stencil with Optimized Dataflow Architecture Compiler☆16Updated 4 years ago
- Graph accelerator on FPGAs and ASICs☆12Updated 6 years ago
- ☆32Updated 2 years ago
- Multi-target compiler for Sum-Product Networks, based on MLIR and LLVM.☆23Updated this week
- ☆13Updated 3 years ago
- Benchmark suite containing cache filtered traces for use with Ramulator. These include some of the workloads used in our SIGMETRICS 2019 …☆19Updated 4 years ago
- PIM-ML is a benchmark for training machine learning algorithms on the UPMEM architecture, which is the first publicly-available real-worl…☆18Updated last year
- HeteroSync is a benchmark suite for performing fine-grained synchronization on tightly coupled GPUs☆27Updated 2 months ago
- Code released to accompany the ISCA paper: "T4: Compiling Sequential Code for Effective Speculative Parallelization in Hardware"☆27Updated 2 years ago
- Replace original DRAM model in GPGPU-sim with Ramulator DRAM model☆17Updated 5 years ago
- ☆13Updated 4 years ago
- A Dataflow library for graph analytics acceleration☆14Updated 8 years ago
- ☆25Updated 3 years ago
- HeteroHalide: From Image Processing DSL to Efficient FPGA Acceleration☆15Updated 4 years ago
- EQueue Dialect☆39Updated 2 years ago
- A Full-System Framework for Simulating NDP devices from Caches to DRAM☆14Updated 10 months ago
- ☆22Updated 5 years ago
- Domain-Specific Architecture Generator 2☆20Updated 2 years ago
- MLSys 2021 paper: MicroRec: efficient recommendation inference by hardware and data structure solutions☆15Updated 3 years ago
- Source code for the architectural and circuit-level simulators used for modeling the CROW (Copy-ROW DRAM) mechanism proposed in our ISCA …☆15Updated 5 years ago
- SMASH is a hardware-software cooperative mechanism that enables highly-efficient indexing and storage of sparse matrices. The key idea of…☆15Updated 4 years ago
- ordspecsim: The Swarm architecture simulator☆24Updated last year
- GARDENIA: Graph Analytics Repository for Designing Efficient Next-generation Accelerators☆30Updated 2 years ago
- High Bandwidth Memory (HBM) timing model based on DRAMSim2☆41Updated 7 years ago
- Heterogeneous simulator for DECADES Project☆29Updated 5 months ago
- CasHMC: A Cycle-accurate Simulator for Hybrid Memory Cube☆20Updated 6 years ago