StanfordAHA / lassen
The PE for the second generation CGRA (garnet).
☆17Updated 4 months ago
Alternatives and similar repositories for lassen:
Users that are interested in lassen are comparing it to the libraries listed below
- ☆10Updated last year
- Peak : Processor Specification Language ala Newell and Bell's ISP☆20Updated last year
- Fast PnR toolchain for CGRA☆18Updated 5 months ago
- Lake is a framework for generating synthesizable memory modules from a high-level behavioral specification and widely-available memory ma…☆20Updated this week
- Collection of test cases for Yosys☆18Updated 3 years ago
- CoreIR Symbolic Analyzer☆63Updated 4 years ago
- ESI is an FPGA connectivity system. It uses typed, latency-insensitive on-chip connections between ESI-enabled modules. It also bridges o…☆34Updated 4 years ago
- Python implementations of fixed size hardware types (Bit, BitVector, UInt, SInt, ...) based on the SMT-LIB2 semantics☆18Updated last year
- A library and command-line tool for querying a Verilog netlist.☆26Updated 2 years ago
- A fault-injection framework using Chisel and FIRRTL☆34Updated last year
- Implementation of the Advanced Encryption Standard in Chisel☆20Updated 2 years ago
- Benchmarks for Yosys development☆23Updated 4 years ago
- ☆15Updated 3 years ago
- Using e-graphs to synthesize netlists from boolean logic.☆14Updated last year
- FPGA acceleration of arbitrary precision floating point computations.☆38Updated 2 years ago
- QuteRTL: A RTL Front-End Towards Intelligent Synthesis and Verification☆14Updated 8 years ago
- Next generation CGRA generator☆108Updated this week
- netlistDB - Intermediate format for digital hardware representation with graph database API☆30Updated 3 years ago
- A home for Genesis2 sources.☆39Updated this week
- Open source fpga project leveraging vtr CAD flow.☆26Updated last year
- Papers, Posters, Presentations, Documentation...☆18Updated last year
- OpenDesign Flow Database☆16Updated 6 years ago
- ☆52Updated 2 years ago
- BSG Replicant: Cosimulation and Emulation Infrastructure for HammerBlade☆29Updated last month
- DASS HLS Compiler☆27Updated last year
- CHIPKIT: An agile, reusable open-source framework for rapid test chip development☆40Updated 4 years ago
- A 32-bit RISC-V Processor Designed with High-Level Synthesis☆50Updated 4 years ago
- An open source generator for standard cell based memories.☆12Updated 8 years ago
- Runtime-First FPGA Interchange Routing Contest @ FPGA’24☆31Updated 2 months ago