Alternatives and similar repositories for lassen

Users that are interested in lassen are comparing it to the libraries listed below

• cdonovick / peak
  Peak : Processor Specification Language ala Newell and Bell's ISP
  ☆20Updated last year
• Kuree / cgra_pnr
  Fast PnR toolchain for CGRA
  ☆18Updated last year
• microsoft / Elastic-Silicon-Interconnect
  ESI is an FPGA connectivity system. It uses typed, latency-insensitive on-chip connections between ESI-enabled modules. It also bridges o…
  ☆34Updated 5 years ago
• rdaly525 / coreir
  ☆104Updated 3 years ago
• vegaluisjose / vast
  Verilog AST
  ☆21Updated last year
• chipsalliance / fpga-interchange-schema
  ☆56Updated 3 years ago
• bespoke-silicon-group / bsg_replicant
  BSG Replicant: Cosimulation and Emulation Infrastructure for HammerBlade
  ☆37Updated 2 months ago
• YosysHQ / yosys-tests
  Collection of test cases for Yosys
  ☆17Updated 3 years ago
• mrc-donato / CHIPKIT-Tutorial
  ☆15Updated 4 years ago
• leonardt / hwtypes
  Python implementations of fixed size hardware types (Bit, BitVector, UInt, SInt, ...) based on the SMT-LIB2 semantics
  ☆18Updated 2 years ago
• mikeurbach / egg-netlist-synthesizer
  Using e-graphs to synthesize netlists from boolean logic.
  ☆14Updated 2 years ago
• StanfordAHA / garnet
  Next generation CGRA generator
  ☆115Updated last week
• IBM / chiffre
  A fault-injection framework using Chisel and FIRRTL
  ☆36Updated last month
• sabbaghm / c-ll-verilog
  An LLVM based mini-C to Verilog High-level Synthesis tool
  ☆39Updated 8 months ago
• StanfordAHA / lake
  Lake is a framework for generating synthesizable memory modules from a high-level behavioral specification and widely-available memory ma…
  ☆22Updated this week
• ymanerka / rtlcheck
  RTLCheck
  ☆22Updated 7 years ago
• scale-lab / la-core
  Linear algebra accelerators for RISC-V (published in ICCD 17)
  ☆67Updated 8 years ago
• leonardt / fault
  A Python package for testing hardware (part of the magma ecosystem)
  ☆46Updated last year
• Kuree / kratos
  Debuggable hardware generator
  ☆70Updated 2 years ago
• sterin / super-prove-build
  ☆13Updated 5 years ago
• HardwareIR / netlistDB
  netlistDB - Intermediate format for digital hardware representation with graph database API
  ☆31Updated 4 years ago
• YosysHQ / yosys-bench
  Benchmarks for Yosys development
  ☆24Updated 5 years ago
• YosysHQ / yosys-bigsim
  A collection of big designs to run post-synthesis simulations with yosys
  ☆49Updated 10 years ago
• leonardt / verilogAST-cpp
  C++17 implementation of an AST for Verilog code generation
  ☆24Updated 2 years ago
• amamory-verification / hw-formal-verif
  Hardware Formal Verification
  ☆16Updated 5 years ago
• Nic30 / hwtHls
  LLVM based HLS library for HWToolkit (hardware devel. toolkit)
  ☆25Updated this week
• cucapra / latte21
  Languages, Tools, and Techniques for Accelerator Design
  ☆33Updated 4 years ago
• spcl / apfp
  FPGA acceleration of arbitrary precision floating point computations.
  ☆40Updated 3 years ago
• YosysHQ / VlogHammer
  A Verilog Synthesis Regression Test
  ☆37Updated last year
• broccolimicro / loom
  design and verification of asynchronous circuits
  ☆41Updated last month