The PE for the second generation CGRA (garnet).
☆18Feb 22, 2026Updated 3 months ago
Alternatives and similar repositories for lassen
Users that are interested in lassen are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- Documentation for the entire CGRAFlow☆19Sep 17, 2021Updated 4 years ago
- Peak : Processor Specification Language ala Newell and Bell's ISP☆21Dec 5, 2023Updated 2 years ago
- Fast PnR toolchain for CGRA☆18Jul 26, 2024Updated last year
- Next generation CGRA generator☆120Updated this week
- Python bindings for coreir☆11Sep 13, 2023Updated 2 years ago
- Virtual machines for every use case on DigitalOcean • AdGet dependable uptime with 99.99% SLA, simple security tools, and predictable monthly pricing with DigitalOcean's virtual machines, called Droplets.
- Python implementations of fixed size hardware types (Bit, BitVector, UInt, SInt, ...) based on the SMT-LIB2 semantics☆18Sep 13, 2023Updated 2 years ago
- ☆62May 15, 2026Updated last week
- An LLVM pass that can generate CDFG and map the target loops onto a parameterizable CGRA.☆80Jan 6, 2026Updated 4 months ago
- Zeonica is a simulator for CGRA and Wafer-Scale Accelerators.☆19May 11, 2026Updated last week
- CoreIR Symbolic Analyzer☆75Oct 27, 2020Updated 5 years ago
- Integration test for entire CGRA flow☆12Jan 17, 2020Updated 6 years ago
- LLVM based HLS library for HWToolkit (hardware devel. toolkit)☆29May 13, 2026Updated last week
- ☆15Mar 17, 2026Updated 2 months ago
- ☆82Feb 7, 2025Updated last year
- AI Agents on DigitalOcean Gradient AI Platform • AdBuild production-ready AI agents using customizable tools or access multiple LLMs through a single endpoint. Create custom knowledge bases or connect external data.
- Open source fpga project leveraging vtr CAD flow.☆26Mar 4, 2023Updated 3 years ago
- Loam system models☆16Dec 30, 2019Updated 6 years ago
- A home for Genesis2 sources.☆47Apr 29, 2026Updated 3 weeks ago
- mantle library☆44Dec 20, 2022Updated 3 years ago
- CS533 Course Project (ongoing) - Exploring Parallel Architectures for Neural Processing Unit Implementations☆22May 4, 2017Updated 9 years ago
- ILA Model Database☆24Sep 27, 2020Updated 5 years ago
- CGRA Compilation Framework☆92Jul 15, 2023Updated 2 years ago
- A header only C++11 library for functional coverage☆35Oct 5, 2022Updated 3 years ago
- OpenMP front-end based on LLVM for CGRAs☆10Oct 2, 2022Updated 3 years ago
- End-to-end encrypted cloud storage - Proton Drive • AdSpecial offer: 40% Off Yearly / 80% Off First Month. Protect your most important files, photos, and documents from prying eyes.
- Coarse Grained Reconfigurable Arrays with Chisel3☆12Jul 1, 2024Updated last year
- An example OMI Device FPGA with 2 DDR4 memory ports☆20Jan 5, 2023Updated 3 years ago
- RISC-V RV32I CPU written in verilog☆10Jul 11, 2020Updated 5 years ago
- Yosys plugin for synthesis of Bluespec code☆15Sep 8, 2021Updated 4 years ago
- A custom coprocessor and SoC for hardware security experiments in electronics.☆12May 20, 2017Updated 9 years ago
- magma circuits☆265Oct 19, 2024Updated last year
- Debuggable hardware generator☆71Feb 17, 2023Updated 3 years ago
- An MLIR dialect to enable the efficient acceleration of ML model on CGRAs.☆67Oct 9, 2024Updated last year
- An integrated CGRA design framework☆92Mar 18, 2025Updated last year
- Deploy open-source AI quickly and easily - Special Bonus Offer • AdRunpod Hub is built for open source. One-click deployment and autoscaling endpoints without provisioning your own infrastructure.
- ESI is an FPGA connectivity system. It uses typed, latency-insensitive on-chip connections between ESI-enabled modules. It also bridges o…☆35Sep 30, 2020Updated 5 years ago
- There are many RISC V projects on iCE40. This one is mine.☆15Jun 25, 2020Updated 5 years ago
- Wrapper for ETH Ariane Core☆22Sep 2, 2025Updated 8 months ago
- Multi-Processor System on Chip with RISCV-32 / RISCV-64 / RISCV-128☆13Updated this week
- BOOM's Simulation Accelerator.☆13Dec 16, 2021Updated 4 years ago
- Lake is a framework for generating synthesizable memory modules from a high-level behavioral specification and widely-available memory ma…☆24May 9, 2026Updated 2 weeks ago
- autorouter forked from https://www-soc.lip6.fr/git/coriolis.git☆15May 21, 2018Updated 8 years ago