yhqiu16 / TRAMLinks
Template-based Reconfigurable Architecture Modeling Framework
☆14Updated 3 years ago
Alternatives and similar repositories for TRAM
Users that are interested in TRAM are comparing it to the libraries listed below
Sorting:
- An integrated CGRA design framework☆90Updated 6 months ago
- A list of our chiplet simulaters☆38Updated 2 months ago
- An Open-Source Tool for CGRA Accelerators☆72Updated last week
- CGRA-Flow is an integrated framework for CGRA compilation, exploration, synthesis, and development.☆137Updated 3 months ago
- A low power platform based on X-HEEP and integrating the ESL-CGRA☆14Updated last week
- The open-sourced version of BOOM-Explorer☆43Updated 2 years ago
- High-Performance Sparse Linear Algebra on HBM-Equipped FPGAs Using HLS☆95Updated 11 months ago
- An Open-Source Tool for CGRA Accelerators☆24Updated this week
- An FPGA accelerator for general-purpose Sparse-Matrix Dense-Matrix Multiplication (SpMM).☆84Updated last year
- ☆58Updated 5 months ago
- A systolic array simulator for multi-cycle MACs and varying-byte words, with the paper accepted to HPCA 2022.☆80Updated 3 years ago
- CGRA Compilation Framework☆87Updated 2 years ago
- [ASAP 2020; FPGA 2020] Hardware architecture to accelerate GNNs (common IP modules for minibatch training and full batch inference)☆41Updated 4 years ago
- TAPA compiles task-parallel HLS program into high-performance FPGA accelerators.☆174Updated last month
- PANDA: Architecture-Level Power Evaluation by Unifying Analytical and Machine Learning Solutions☆16Updated last year
- ☆42Updated 3 months ago
- gem5 repository to study chiplet-based systems☆81Updated 6 years ago
- MAERI: A DNN accelerator with reconfigurable interconnects to support flexible dataflow (http://synergy.ece.gatech.edu/tools/maeri/)☆66Updated 3 years ago
- Release of stream-specialization software/hardware stack.☆121Updated 2 years ago
- CHARM: Composing Heterogeneous Accelerators on Heterogeneous SoC Architecture☆155Updated this week
- An MLIR Complier for PyTorch/C/C++ Codes into HLS Dataflow Designs☆47Updated last month
- Simulator framework for analysis of performance, energy consumption, area and cost of multi-node multi-chiplet tile-based manycore design…☆69Updated last year
- A RISC-V BOOM Microarchitecture Power Modeling Framework☆29Updated 2 years ago
- OpenCGRA is an open-source framework for modeling, testing, and evaluating CGRAs.☆158Updated 2 years ago
- ☆13Updated 2 years ago
- RTL implementation of Flex-DPE.☆110Updated 5 years ago
- [FPGA 2021, Best Paper Award] An automated floorplanning and pipelining tool for Vivado HLS.☆124Updated 2 years ago
- A Reconfigurable Accelerator with Data Reordering Support for Low-Cost On-Chip Dataflow Switching☆63Updated 3 weeks ago
- Benchmarks for Accelerator Design and Customized Architectures☆129Updated 5 years ago
- A toolchain for rapid design space exploration of chiplet architectures☆59Updated last month