Alternatives and similar repositories for TRAM

Users that are interested in TRAM are comparing it to the libraries listed below

• pku-dasys / pillars
  An integrated CGRA design framework
  ☆90Updated 4 months ago
• FCAS-LAB / chiplet_simulators
  A list of our chiplet simulaters
  ☆33Updated last month
• ecolab-nus / morpher
  An Open-Source Tool for CGRA Accelerators
  ☆67Updated 3 months ago
• tancheng / CGRA-Flow
  CGRA-Flow is an integrated framework for CGRA compilation, exploration, synthesis, and development.
  ☆135Updated last month
• baichen318 / boom-explorer-public
  The open-sourced version of BOOM-Explorer
  ☆43Updated 2 years ago
• ecolab-nus / morpher-v2
  An Open-Source Tool for CGRA Accelerators
  ☆23Updated last year
• UIUC-ChenLab / ScaleHLS-HIDA
  ☆56Updated 4 months ago
• GraphSAINT / GNN-ARCH
  [ASAP 2020; FPGA 2020] Hardware architecture to accelerate GNNs (common IP modules for minibatch training and full batch inference)
  ☆41Updated 4 years ago
• esl-epfl / HEEPsilon
  A low power platform based on X-HEEP and integrating the ESL-CGRA
  ☆13Updated 10 months ago
• cornell-zhang / HiSparse
  High-Performance Sparse Linear Algebra on HBM-Equipped FPGAs Using HLS
  ☆94Updated 10 months ago
• GT-CHIPS / gem5_chips
  gem5 repository to study chiplet-based systems
  ☆78Updated 6 years ago
• hkust-zhiyao / PANDA
  PANDA: Architecture-Level Power Evaluation by Unifying Analytical and Machine Learning Solutions
  ☆16Updated last year
• linghaosong / Sextans
  An FPGA accelerator for general-purpose Sparse-Matrix Dense-Matrix Multiplication (SpMM).
  ☆81Updated last year
• UCLA-VAST / AutoBridge
  [FPGA 2021, Best Paper Award] An automated floorplanning and pipelining tool for Vivado HLS.
  ☆122Updated 2 years ago
• diwu1990 / uSystolic-Sim
  A systolic array simulator for multi-cycle MACs and varying-byte words, with the paper accepted to HPCA 2022.
  ☆80Updated 3 years ago
• georgia-tech-synergy-lab / SIGMA
  RTL implementation of Flex-DPE.
  ☆108Updated 5 years ago
• maeri-project / MAERI_bsv
  MAERI: A DNN accelerator with reconfigurable interconnects to support flexible dataflow (http://synergy.ece.gatech.edu/tools/maeri/)
  ☆64Updated 3 years ago
• zhaijw18 / mcpat-calib-public
  A RISC-V BOOM Microarchitecture Power Modeling Framework
  ☆27Updated 2 years ago
• hngenc / stellar
  ☆30Updated 9 months ago
• rapidstream-org / rapidstream-tapa
  RapidStream TAPA compiles task-parallel HLS program into high-frequency FPGA accelerators.
  ☆173Updated last week
• UIUC-ChenLab / Nimblock
  ☆13Updated 2 years ago
• pnnl / OpenCGRA
  OpenCGRA is an open-source framework for modeling, testing, and evaluating CGRAs.
  ☆155Updated 2 years ago
• Yinxiao-Feng / chiplet-network-sim
  ☆38Updated 2 months ago
• UCLA-VAST / AutoSA
  AutoSA: Polyhedral-Based Systolic Array Compiler
  ☆221Updated 2 years ago
• MPSLab-ASU / ccf
  CGRA Compilation Framework
  ☆84Updated 2 years ago
• UCLA-VAST / Stream-HLS
  An MLIR Complier for PyTorch/C/C++ Codes into HLS Dataflow Designs
  ☆44Updated last week
• gkrish19 / SIAM-Chiplet-based-Scalable-In-Memory-Acceleration-with-Mesh-for-Deep-Neural-Networks
  A comprehensive tool that allows for system-level performance estimation of chiplet-based In-Memory computing (IMC) architectures.
  ☆23Updated last year
• ecolab-nus / Morpher_CGRA_Mapper
  ☆17Updated 3 months ago
• PrincetonUniversity / muchiSim
  Simulator framework for analysis of performance, energy consumption, area and cost of multi-node multi-chiplet tile-based manycore design…
  ☆68Updated last year
• PolyArch / dsa-framework
  Release of stream-specialization software/hardware stack.
  ☆121Updated 2 years ago