B-Lang-org / bsc
Bluespec Compiler (BSC)
☆996Updated last week
Alternatives and similar repositories for bsc:
Users that are interested in bsc are comparing it to the libraries listed below
- Flexible Intermediate Representation for RTL☆740Updated 7 months ago
- FireSim: Fast and Effortless FPGA-accelerated Hardware Simulation with On-Prem and Cloud Flexibility☆919Updated 2 weeks ago
- RISC-V Formal Verification Framework☆596Updated 3 years ago
- RISC-V CPU, simple 5-stage in-order pipeline, for low-end applications needing MMUs and some performance☆366Updated last year
- RSD: RISC-V Out-of-Order Superscalar Processor☆1,065Updated last month
- SonicBOOM: The Berkeley Out-of-Order Machine☆1,862Updated last week
- educational microarchitectures for risc-v isa☆711Updated last month
- RISC-V CPU, simple 3-stage pipeline, for low-end applications (e.g., embedded, IoT)☆322Updated 3 years ago
- Digital Design with Chisel☆824Updated last week
- SERV - The SErial RISC-V CPU☆1,551Updated 3 weeks ago
- Ibex is a small 32 bit RISC-V CPU core, previously known as zero-riscy.☆1,512Updated 2 weeks ago
- Simple RISC-V 3-stage Pipeline in Chisel☆569Updated 8 months ago
- Linux on LiteX-VexRiscv☆625Updated 3 weeks ago
- VeeR EH1 core☆867Updated last year
- SystemVerilog to Verilog conversion☆613Updated last week
- ☆972Updated last week
- Hardware Description Languages☆1,015Updated 2 months ago
- A Linux-capable RISC-V multicore for and by the world☆674Updated last month
- Package manager and build abstraction tool for FPGA/ASIC development☆1,265Updated last week
- 32-bit Superscalar RISC-V CPU☆989Updated 3 years ago
- Sail RISC-V model☆524Updated last week
- An abstraction library for interfacing EDA tools☆675Updated last week
- Modular hardware build system☆973Updated this week
- chisel tutorial exercises and answers☆720Updated 3 years ago
- A small, light weight, RISC CPU soft core☆1,378Updated 2 months ago
- Scala based HDL☆1,766Updated this week
- CV32E40P is an in-order 4-stage RISC-V RV32IMFCXpulp CPU based on RI5CY from PULP-Platform☆1,045Updated 2 months ago
- A Just-In-Time Compiler for Verilog from VMware Research☆444Updated 3 years ago
- An Agile RISC-V SoC Design Framework with in-order cores, out-of-order cores, accelerators, and more☆1,812Updated this week
- Portable RISC-V System-on-Chip implementation: RTL, debugger and simulators☆649Updated 5 months ago