B-Lang-org / bscLinks
Bluespec Compiler (BSC)
☆1,061Updated 2 weeks ago
Alternatives and similar repositories for bsc
Users that are interested in bsc are comparing it to the libraries listed below
Sorting:
- Flexible Intermediate Representation for RTL☆748Updated last year
- RISC-V CPU, simple 5-stage in-order pipeline, for low-end applications needing MMUs and some performance☆374Updated 2 years ago
- RISC-V Formal Verification Framework☆617Updated 3 years ago
- RSD: RISC-V Out-of-Order Superscalar Processor☆1,128Updated last month
- Sail RISC-V model☆629Updated this week
- SymbiYosys (sby) -- Front-end for Yosys-based formal verification flows☆480Updated last week
- RISC-V CPU, simple 3-stage pipeline, for low-end applications (e.g., embedded, IoT)☆328Updated 3 years ago
- A Linux-capable RISC-V multicore for and by the world☆748Updated 3 weeks ago
- Digital Design with Chisel☆878Updated last week
- Modular hardware build system☆1,108Updated this week
- SERV - The SErial RISC-V CPU☆1,701Updated last month
- SystemVerilog to Verilog conversion☆677Updated last week
- FireSim: Fast and Effortless FPGA-accelerated Hardware Simulation with On-Prem and Cloud Flexibility☆978Updated 5 months ago
- VeeR EH1 core☆912Updated 2 years ago
- Ibex is a small 32 bit RISC-V CPU core, previously known as zero-riscy.☆1,686Updated last week
- A small, light weight, RISC CPU soft core☆1,480Updated 3 months ago
- Low Level Hardware Description — A foundation for building hardware design tools.☆422Updated 3 years ago
- The OpenPiton Platform☆746Updated 2 months ago
- Scala based HDL☆1,889Updated last week
- FOSS Flow For FPGA☆413Updated 10 months ago
- Hardware Description Languages☆1,082Updated 4 months ago
- BaseJump STL: A Standard Template Library for SystemVerilog☆622Updated 2 weeks ago
- mor1kx - an OpenRISC 1000 processor IP core☆566Updated 3 months ago
- SonicBOOM: The Berkeley Out-of-Order Machine☆2,019Updated 6 months ago
- ☆1,087Updated last week
- SystemVerilog parser library fully compliant with IEEE 1800-2017☆453Updated last month
- CV32E40P is an in-order 4-stage RISC-V RV32IMFCXpulp CPU based on RI5CY from PULP-Platform☆1,144Updated 6 months ago
- The CORE-V CVA6 is a highly configurable, 6-stage RISC-V core for both application and embedded applications. Application class configura…☆2,697Updated this week
- Package manager and build abstraction tool for FPGA/ASIC development☆1,367Updated this week
- An abstraction library for interfacing EDA tools☆724Updated 2 weeks ago