Bluespec Compiler (BSC)
☆1,111May 15, 2026Updated last week
Alternatives and similar repositories for bsc
Users that are interested in bsc are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- Main page☆133Feb 12, 2020Updated 6 years ago
- RISC-V CPU, simple 3-stage pipeline, for low-end applications (e.g., embedded, IoT)☆338Jan 23, 2022Updated 4 years ago
- RISC-V CPU, simple 5-stage in-order pipeline, for low-end applications needing MMUs and some performance☆381Oct 19, 2023Updated 2 years ago
- A generic test bench written in Bluespec☆57Dec 15, 2020Updated 5 years ago
- A core language for rule-based hardware design 🦑☆173Dec 10, 2025Updated 5 months ago
- End-to-end encrypted email - Proton Mail • AdSpecial offer: 40% Off Yearly / 80% Off First Month. All Proton services are open source and independently audited for security.
- A collection of common Bluespec interfaces/modules.☆103Apr 19, 2024Updated 2 years ago
- A place to share libraries and utilities that don't belong in the core bsc repo☆40May 1, 2026Updated 3 weeks ago
- RISC-V Core; superscalar, out-of-order, multi-core capable; based on RISCY-OOO from MIT☆187Apr 4, 2026Updated last month
- Haskell to VHDL/Verilog/SystemVerilog compiler☆1,597Updated this week
- Textbook and full source codes to learn basics of RISC-V pipelined CPU design using the Bluespec Hardware Design Language(s)☆99Oct 17, 2025Updated 7 months ago
- BSC Development Workstation (BDW)☆33May 1, 2026Updated 3 weeks ago
- Bluespec BSV HLHDL tutorial☆115Mar 29, 2016Updated 10 years ago
- Tutorial on hardware design using Bluespec BH (Bluespec Classic) for Haskell programmers at ACM ICFP 2020 conference☆79Nov 24, 2022Updated 3 years ago
- Haskell library for hardware description☆106Aug 18, 2025Updated 9 months ago
- Virtual machines for every use case on DigitalOcean • AdGet dependable uptime with 99.99% SLA, simple security tools, and predictable monthly pricing with DigitalOcean's virtual machines, called Droplets.
- XLS: Accelerated HW Synthesis☆1,493Updated this week
- Connectal is a framework for software-driven hardware development.☆178Oct 16, 2023Updated 2 years ago
- Main page☆33Feb 12, 2020Updated 6 years ago
- A Platform for High-Level Parametric Hardware Specification and its Modular Verification☆167May 4, 2026Updated 3 weeks ago
- Hardware Description Languages☆1,148Apr 6, 2026Updated last month
- Verible is a suite of SystemVerilog developer tools, including a parser, style-linter, formatter and language server☆1,846Mar 13, 2026Updated 2 months ago
- Scala based HDL☆1,988May 9, 2026Updated 2 weeks ago
- SystemVerilog 2017 Pre-processor, Parser, Elaborator, UHDM Compiler. Provides IEEE Design/TB C/C++ VPI and Python AST & UHDM APIs. Compil…☆460May 20, 2026Updated last week
- Yosys Open SYnthesis Suite☆4,464Updated this week
- Managed Database hosting by DigitalOcean • AdPostgreSQL, MySQL, MongoDB, Kafka, Valkey, and OpenSearch available. Automatically scale up storage and focus on building your apps.
- Circuit IR Compilers and Tools☆2,129May 19, 2026Updated last week
- Flexible Intermediate Representation for RTL☆750Aug 20, 2024Updated last year
- Build Customized FPGA Implementations for Vivado☆376Updated this week
- Chisel: A Modern Hardware Design Language☆4,668Updated this week
- A standalone parser for BSV (Bluespec SystemVerilog) written in Go☆14Dec 20, 2016Updated 9 years ago
- Verilator open-source SystemVerilog simulator and lint system☆3,622May 20, 2026Updated last week
- SystemVerilog compiler and language services☆1,049Updated this week
- Hardware generator debugger☆77Feb 12, 2024Updated 2 years ago
- SystemVerilog to Verilog conversion☆728Mar 28, 2026Updated last month
- Wordpress hosting with auto-scaling - Free Trial Offer • AdFully Managed hosting for WordPress and WooCommerce businesses that need reliable, auto-scalable performance. Cloudways SafeUpdates now available.
- Formal semantics of BSV (Bluespec SystemVerilog), given as a Haskell Program and accompanying document☆18Jul 17, 2016Updated 9 years ago
- 一篇全面的 Bluespec SystemVerilog (BSV) 中文教程，介绍了BSV的调度、FIFO数据流、多态等高级特性，展示了BSV相比于传统Verilog开发的优势。☆609Sep 15, 2023Updated 2 years ago
- A hardware compiler based on LLHD and CIRCT☆270Jun 30, 2025Updated 10 months ago
- Low Level Hardware Description — A foundation for building hardware design tools.☆434Apr 20, 2022Updated 4 years ago
- An abstraction library for interfacing EDA tools☆770Apr 24, 2026Updated last month
- Package manager and build abstraction tool for FPGA/ASIC development☆1,417May 10, 2026Updated 2 weeks ago
- SymbiYosys (sby) -- Front-end for Yosys-based formal verification flows☆510May 12, 2026Updated 2 weeks ago