B-Lang-org / bscView external linksLinks
Bluespec Compiler (BSC)
☆1,077Jan 28, 2026Updated 2 weeks ago
Alternatives and similar repositories for bsc
Users that are interested in bsc are comparing it to the libraries listed below
Sorting:
- Main page☆129Feb 12, 2020Updated 6 years ago
- RISC-V CPU, simple 3-stage pipeline, for low-end applications (e.g., embedded, IoT)☆331Jan 23, 2022Updated 4 years ago
- RISC-V CPU, simple 5-stage in-order pipeline, for low-end applications needing MMUs and some performance☆376Oct 19, 2023Updated 2 years ago
- Haskell to VHDL/Verilog/SystemVerilog compiler☆1,582Updated this week
- RISC-V Core; superscalar, out-of-order, multi-core capable; based on RISCY-OOO from MIT☆184May 8, 2025Updated 9 months ago
- A collection of common Bluespec interfaces/modules.☆103Apr 19, 2024Updated last year
- A core language for rule-based hardware design 🦑☆171Dec 10, 2025Updated 2 months ago
- A place to share libraries and utilities that don't belong in the core bsc repo☆38Jan 10, 2026Updated last month
- XLS: Accelerated HW Synthesis☆1,426Updated this week
- A generic test bench written in Bluespec☆57Dec 15, 2020Updated 5 years ago
- BSC Development Workstation (BDW)☆32Nov 9, 2025Updated 3 months ago
- Bluespec BSV HLHDL tutorial☆111Mar 29, 2016Updated 9 years ago
- Tutorial on hardware design using Bluespec BH (Bluespec Classic) for Haskell programmers at ACM ICFP 2020 conference☆77Nov 24, 2022Updated 3 years ago
- Haskell library for hardware description☆106Aug 18, 2025Updated 5 months ago
- A Platform for High-Level Parametric Hardware Specification and its Modular Verification☆164Nov 20, 2025Updated 2 months ago
- Yosys Open SYnthesis Suite☆4,272Updated this week
- Scala based HDL☆1,922Updated this week
- Verible is a suite of SystemVerilog developer tools, including a parser, style-linter, formatter and language server☆1,769Dec 22, 2025Updated last month
- SystemVerilog 2017 Pre-processor, Parser, Elaborator, UHDM Compiler. Provides IEEE Design/TB C/C++ VPI and Python AST & UHDM APIs. Compil…☆445Sep 6, 2025Updated 5 months ago
- Connectal is a framework for software-driven hardware development.☆176Oct 16, 2023Updated 2 years ago
- Hardware Description Languages☆1,112Jul 14, 2025Updated 7 months ago
- Textbook and full source codes to learn basics of RISC-V pipelined CPU design using the Bluespec Hardware Design Language(s)☆92Oct 17, 2025Updated 3 months ago
- Circuit IR Compilers and Tools☆2,031Updated this week
- Flexible Intermediate Representation for RTL☆748Aug 20, 2024Updated last year
- Build Customized FPGA Implementations for Vivado☆355Updated this week
- Hardware generator debugger☆77Feb 12, 2024Updated 2 years ago
- Chisel: A Modern Hardware Design Language☆4,567Updated this week
- SystemVerilog to Verilog conversion☆701Nov 24, 2025Updated 2 months ago
- A hardware compiler based on LLHD and CIRCT☆265Jun 30, 2025Updated 7 months ago
- A modern hardware definition language and toolchain based on Python☆1,906Jan 26, 2026Updated 2 weeks ago
- SystemVerilog compiler and language services☆948Updated this week
- Main page☆32Feb 12, 2020Updated 6 years ago
- Verilator open-source SystemVerilog simulator and lint system☆3,356Updated this week
- RISC-V Formal Verification Framework☆624Apr 6, 2022Updated 3 years ago
- An abstraction library for interfacing EDA tools☆750Updated this week
- Low Level Hardware Description — A foundation for building hardware design tools.☆426Apr 20, 2022Updated 3 years ago
- Package manager and build abstraction tool for FPGA/ASIC development☆1,387Updated this week
- SymbiYosys (sby) -- Front-end for Yosys-based formal verification flows☆490Feb 4, 2026Updated last week
- magma circuits☆265Oct 19, 2024Updated last year