Bluespec Compiler (BSC)
☆1,127Jul 4, 2026Updated this week
Alternatives and similar repositories for bsc
Users that are interested in bsc are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- Main page☆133Feb 12, 2020Updated 6 years ago
- RISC-V CPU, simple 3-stage pipeline, for low-end applications (e.g., embedded, IoT)☆339Jan 23, 2022Updated 4 years ago
- RISC-V CPU, simple 5-stage in-order pipeline, for low-end applications needing MMUs and some performance☆382Oct 19, 2023Updated 2 years ago
- A generic test bench written in Bluespec☆57Dec 15, 2020Updated 5 years ago
- A core language for rule-based hardware design 🦑☆175Dec 10, 2025Updated 6 months ago
- Open source password manager - Proton Pass • AdSecurely store, share, and autofill your credentials with Proton Pass, the end-to-end encrypted password manager trusted by millions.
- A collection of common Bluespec interfaces/modules.☆104Apr 19, 2024Updated 2 years ago
- A place to share libraries and utilities that don't belong in the core bsc repo☆40May 1, 2026Updated 2 months ago
- RISC-V Core; superscalar, out-of-order, multi-core capable; based on RISCY-OOO from MIT☆187Apr 4, 2026Updated 3 months ago
- Haskell to VHDL/Verilog/SystemVerilog compiler☆1,596Updated this week
- Textbook and full source codes to learn basics of RISC-V pipelined CPU design using the Bluespec Hardware Design Language(s)☆102Updated this week
- BSC Development Workstation (BDW)☆33May 1, 2026Updated 2 months ago
- Bluespec BSV HLHDL tutorial☆116Mar 29, 2016Updated 10 years ago
- Tutorial on hardware design using Bluespec BH (Bluespec Classic) for Haskell programmers at ACM ICFP 2020 conference☆79Nov 24, 2022Updated 3 years ago
- Haskell library for hardware description☆106Aug 18, 2025Updated 10 months ago
- Managed hosting for WordPress and PHP on Cloudways • AdManaged hosting for WordPress, Magento, Laravel, or PHP apps, on multiple cloud providers. Deploy in minutes on Cloudways by DigitalOcean.
- XLS: Accelerated HW Synthesis☆1,503Updated this week
- Connectal is a framework for software-driven hardware development.☆179Oct 16, 2023Updated 2 years ago
- Main page☆33Feb 12, 2020Updated 6 years ago
- A Platform for High-Level Parametric Hardware Specification and its Modular Verification☆167May 26, 2026Updated last month
- Hardware Description Languages☆1,158Apr 6, 2026Updated 3 months ago
- Verible is a suite of SystemVerilog developer tools, including a parser, style-linter, formatter and language server☆1,877Jun 22, 2026Updated 2 weeks ago
- Scala based HDL☆2,012Jun 20, 2026Updated 2 weeks ago
- SystemVerilog 2017 Pre-processor, Parser, Elaborator, UHDM Compiler. Provides IEEE Design/TB C/C++ VPI and Python AST & UHDM APIs. Compil…☆464Updated this week
- Yosys Open SYnthesis Suite☆4,566Updated this week
- Deploy on Railway without the complexity - Free Credits Offer • AdConnect your repo and Railway handles the rest with instant previews. Quickly provision container image services, databases, and storage volumes.
- Circuit IR Compilers and Tools☆2,173Updated this week
- Flexible Intermediate Representation for RTL☆748Aug 20, 2024Updated last year
- Build Customized FPGA Implementations for Vivado☆382Jun 27, 2026Updated last week
- Chisel: A Modern Hardware Design Language☆4,701Jun 28, 2026Updated last week
- A standalone parser for BSV (Bluespec SystemVerilog) written in Go☆14Dec 20, 2016Updated 9 years ago
- Verilator open-source SystemVerilog simulator and lint system☆3,707Updated this week
- Hardware generator debugger☆79Feb 12, 2024Updated 2 years ago
- SystemVerilog compiler and language services☆1,078Jun 27, 2026Updated last week
- SystemVerilog to Verilog conversion☆739Mar 28, 2026Updated 3 months ago
- Deploy to Railway using AI coding agents - Free Credits Offer • AdUse Claude Code, Codex, OpenCode, and more. Autonomous software development now has the infrastructure to match with Railway.
- Formal semantics of BSV (Bluespec SystemVerilog), given as a Haskell Program and accompanying document☆17Jul 17, 2016Updated 9 years ago
- 一篇全面的 Bluespec SystemVerilog (BSV) 中文教程，介绍了BSV的调度、FIFO数据流、多态等高级特性，展示了BSV相比于传统Verilog开发的优势。☆610Sep 15, 2023Updated 2 years ago
- A hardware compiler based on LLHD and CIRCT☆270Jun 30, 2025Updated last year
- Low Level Hardware Description — A foundation for building hardware design tools.☆434Apr 20, 2022Updated 4 years ago
- An abstraction library for interfacing EDA tools☆774Updated this week
- Package manager and build abstraction tool for FPGA/ASIC development☆1,429Updated this week
- SymbiYosys (sby) -- Front-end for Yosys-based formal verification flows☆525Jun 23, 2026Updated last week