B-Lang-org / bscLinks
Bluespec Compiler (BSC)
☆1,072Updated this week
Alternatives and similar repositories for bsc
Users that are interested in bsc are comparing it to the libraries listed below
Sorting:
- Flexible Intermediate Representation for RTL☆749Updated last year
- RISC-V Formal Verification Framework☆621Updated 3 years ago
- RISC-V CPU, simple 5-stage in-order pipeline, for low-end applications needing MMUs and some performance☆374Updated 2 years ago
- Sail RISC-V model☆645Updated this week
- RSD: RISC-V Out-of-Order Superscalar Processor☆1,145Updated 2 weeks ago
- SERV - The SErial RISC-V CPU☆1,726Updated last week
- Digital Design with Chisel☆889Updated last month
- VeeR EH1 core☆918Updated 2 years ago
- SymbiYosys (sby) -- Front-end for Yosys-based formal verification flows☆485Updated last week
- FireSim: Fast and Effortless FPGA-accelerated Hardware Simulation with On-Prem and Cloud Flexibility☆984Updated 6 months ago
- A Linux-capable RISC-V multicore for and by the world☆754Updated 2 months ago
- SystemVerilog to Verilog conversion☆693Updated last month
- RISC-V CPU, simple 3-stage pipeline, for low-end applications (e.g., embedded, IoT)☆329Updated 3 years ago
- FOSS Flow For FPGA☆420Updated last year
- Modular hardware build system☆1,119Updated this week
- educational microarchitectures for risc-v isa☆729Updated 4 months ago
- Ibex is a small 32 bit RISC-V CPU core, previously known as zero-riscy.☆1,735Updated 3 weeks ago
- A small, light weight, RISC CPU soft core☆1,496Updated last month
- The OpenPiton Platform☆758Updated 3 months ago
- Scala based HDL☆1,903Updated this week
- ☆628Updated this week
- Hardware Description Languages☆1,092Updated 5 months ago
- Intermediate Language (IL) for Hardware Accelerator Generators☆573Updated this week
- Low Level Hardware Description — A foundation for building hardware design tools.☆426Updated 3 years ago
- ☆1,107Updated this week
- Working Draft of the RISC-V Debug Specification Standard☆502Updated 2 weeks ago
- VRoom! RISC-V CPU☆514Updated last year
- mor1kx - an OpenRISC 1000 processor IP core☆570Updated 4 months ago
- Verible is a suite of SystemVerilog developer tools, including a parser, style-linter, formatter and language server☆1,737Updated 3 weeks ago
- BaseJump STL: A Standard Template Library for SystemVerilog☆632Updated 3 weeks ago